JPS632344A - Detecting method for wafer chip - Google Patents

Abstract

PURPOSE:To recognize an actual array by simultaneously recognizing a plurality of wafer chips by one visual detection, detecting the positional relationship of a plurality of wafer chips of reference and a pitch between the chips, and moving the recognized position while correcting the recognized position to detect it, thereby eliminating the intermediary of an operator. CONSTITUTION:A wafer ring 14 having aligned wafer chips 11 is secured on an XY table 15, the chips 11 are picked up by an ITV camera 1, the image is processed by the picked image signal by means of a recognition unit 2, the result is transferred by a communication channel 3 to a die bonder controller 4 to control the table 15 to the recognition position and pickup position of the chips 11. Four wafer chips are simultaneously recognized at the recognition position initially given by an operator, the table 15 is moved by the pickup unit of the chips from the recognition result, the chips are mounted, next recognition position is then calculated including a pitch correction, the table 15 is moved, and similarly recognized. These operations are repeated to mount the chips.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for detecting wafer chips by visual recognition in an automatic electronic component mounting machine such as a die bonder.

(Background Art) A wafer chip is obtained by cutting a disk-shaped wafer on which a large number of semiconductor circuits are formed into a lattice shape for each semiconductor circuit, and as shown in FIG. After placing the wafer 10 on the transparent sheet 12 and cutting it into a grid shape with a cutter (not shown), the expand ring 13 serving as the base of the transparent sheet 12 with adhesive is expanded, as shown in FIG. The individual wafer chips 11 are separated so that they can be mounted using a die bonder or the like.

However, since wafer chips are manufactured as described above, they include the following irregularities. That is, (1) Since the wafer is circular, the wafer chips on the end surface do not have a uniform shape. Further, the number of wafer chips in the horizontal and vertical directions is also non-uniform.

■Some wafer chips are chipped when cutting the wafer.

Cracks may occur.

■When stretching the sea urchin, the stretching rate between wafer chips varies, and the pitch between the wafer chips may become uneven.

etc.

For this reason, in automatic mounting machines such as dieponders that mount wafer chips, it is necessary to confirm the wafer chips by visual recognition in order to meet the required positional brightness, and the wafer chips are It is necessary to determine whether the shape of the chip is good or not and to detect the extraction position.

Figure 9 shows the conventional recognition method. Prior to recognition, the operator provides (1) recognition start position (chip center of any wafer chip) and (2) pitch between wafer chips as data. .

The operation is performed as follows.

(2) First, the wafer chip is recognized at the recognition position given by the operator (step 201), and the quality of the shape is determined to determine whether or not it can be mounted (step 202).

■If mounting is possible, detect the position of the wafer chip, mount it (step 203), and move to the next recognition position according to the pitch data given by the operator.Step 2
04), recognition is performed in the same manner (step 201).

■If not mounted, do not mount and move to the next recognition position (step 204), perform recognition again (step 20)
1).

Repeat steps 0 or more to mount wafer chips.

However, when the wafer chips 11 are arranged at a constant pitch p as shown in FIG. 10(a), the wafer chips 11 cannot be repeatedly detected within the recognition area A. , no problem arises, but Figure 1O (b),
If the stretching rate of the wafer chip 11 varies as shown in (c), or if the wafer chip 11 is tilted as a whole, the wafer chip 11 cannot be detected within the recognition area A, and the detection is interrupted and the operator It was necessary to correct the pitch data or correct the tilt of the wafer chip.

Furthermore, the above method requires re-recognition when a defective wafer chip is detected, which poses a problem of impact on mounting takt time. In other words, if the wafer chip is a good product, it can be mounted after recognition, but if it is a defective chip, the mounting must be postponed until a good product is detected, making it impossible to perform the mounting at a predetermined rhythm. .

On the other hand, FIG. 11 shows a conventional method for determining the end of row recognition (a state in which recognition of one row of wafer chips has been completed), in which (to) −Gψ→(v )
When it is determined that the product is defective or has no chip three times in a row, it is determined that the row recognition has ended. In addition, FIG. 11 (b) is a flowchart of the process, in which it is determined in step 205 that defective products or no chips occur three times in a row, and if the result is YES, step 206 is performed.
It was determined that row recognition had finished.

In addition, Fig. 12 shows a method for determining whether all recognition has been completed (recognition of all wafer chips has been completed). Branch) → (5
), when it is determined that 6 consecutive defective products or no chips are found after the completion of row recognition, it is determined that all recognition has been completed. In addition, FIG. 12 (B) is a flowchart, in which it is determined in step 207 that defective products or no chips occur six times in a row after the completion of column wt recognition, and if the result is YES, all recognition is performed in step 208.
I thought it was over on November 11th.

However, the number of recognitions required to determine whether row recognition is complete or all recognition is complete is large, which affects the mounting takt time.

(Objective of the Invention) The present invention has been proposed in view of the above points, and eliminates operator intervention by automatically correcting the recognition position, and also reduces the mounting tact by re-J m etc. for defective wafer chips. The purpose of the present invention is to provide a method for detecting wafer chips that can eliminate the influence on wafer chips.

(Disclosure of invention) The present invention will now be described in detail with reference to the drawings showing embodiments.

FIG. 1 shows the configuration of a system embodying the present invention, in which a Unihachi ring 14 on which wafer chips 11 are lined up is fixed on an XY child table 5, and the wafer chips 11 are placed on an ITV.
An image is taken by a camera 1, image processing is performed by a recognition device 2 based on the image signal, and the recognition result is transferred to a die bonder controller 4 through a communication line 3 such as an R3-232G line, and is transferred to the recognition position and take-out position of the wafer chip 11 in the XY direction. The child table 5 is controlled.

Hereinafter, the method for detecting wafer chips according to the present invention will be described assuming that the number of wafer chips to be simultaneously recognized is four.

Figure 2 shows the process of recognition and mounting.Prior to recognition, the operator provides (1) the recognition start position (center of four wafer chips) as data.

In step 10, four wafer chips are initially recognized at the recognition position given by the operator.
2), Regardless of the number of good chips, for example, one good chip is mounted.Step 103), From the recognition result, calculate the next recognition position including pitch correction.Step 104
), move the XY child table 5 (step 101),
Recognition is similarly performed (step 102). These operations are then repeated to mount the wafer chips.

Figure 3 shows the state of recognition; (a) shows when the wafer chips 11 are aligned at a constant pitch, and (b) shows when the stretching rate of the wafer chips 11 varies and the pitch is shifted. In the case (c), the entire sea urchin eight chip 11 is tilted.

Therefore, the four wafer chips 11a recognized at the same time,
Since the chip center 〇 of the next four wafer chips is calculated from llb, lle, and lld, correction is applied, and recognition area A is moved, there is no possibility that a wafer chip cannot be detected within recognition area A. It is something.

Next, a method of calculating the wafer chip takeout position and the center of the recognition area in the next recognition will be explained.

Figure 4 shows four wafer chips lla in recognition area A,
llb, llc, and lid are shown, and C is the center for recognition (recognition center), C,,C,.

C3,c, are wafer chips lla, llb, lie
, lld center of gravity position C/ is four wafer chips ll
a, llb.

11c, the actual center of the lid (4-chip center). Note that c, , C2, C3, C4, and c' are vectors indicating relative positions with respect to the center.

Through image processing, four wafer chips lla,
Center of gravity position C,,C2, of llb, lie, lid
C.

Since C4 is measured, the take-out position by the die bonder is determined as follows, and a good Ueno λ chip is mounted.

11a:C+C 11b:C+C 11e: C+C.

lid:C+04 Also, the 4-chip center C' is (C'= (([:, +(C2+C3+(C4)/4
You can find it by Note that C' indicates the deviation between the recognition center and the centers of the four wafer chips.

Therefore, the center of the next recognition position is determined by the following equation.

X component: Cx+C'8+2Px Y component: C, +C', Note that cx, c' is the X component of c, c', and CY.

C'7 represents the Y component of c and c'. Also,
Px in the above equation is the pitch between 1 chip per chip in the Therefore, P8 multiplied by 2 is added.

Next, the above recognition is repeated along one column, and when it is determined that the column recognition has ended, the next recognition position is calculated using the following equation.

X component: Cx-C'x-2Px Y component: C, -C', +2 PY Note that P7 in the above equation is the pitch between wafer chips in the Y-axis direction, and P (C8Y-C37+C2,, −C4v)/2. Then, based on this calculation result, the recognition position is moved in the vertical direction, and then the recognition position is moved in the horizontal direction again. Note that the horizontal movement direction after turning back is opposite to the previous direction, so the next recognition position is determined by the following equation %.

11b, lie, 1id (7) Center of gravity position (C,,C
2, C3, C41! , C', Px, and PY cannot be calculated if there is a defect or at the end of the column, since all four wafer chips exist in recognition area A and can only be obtained if the wafer chip is of good shape. , In such a case, the previously detected (C', Px, P, is used.

However, the above operation is repeated until it is determined that all recognition has been completed, and each time, for example, one wafer chip is mounted for the four wafer chips that are recognized simultaneously. Even when the recognition area is approaching or at the edge of the wafer, wafer chips that have already been determined to be good in the previous recognition (their positions are stored in the buffer in the die bonder controller 4) can be mounted, reducing the mounting tact time. You can proceed with your work without disturbing the environment.

In the actual recognition, in addition to the data indicating the above-mentioned position, the state of the wafer chip is detected, such as: (1) chip in good shape, (2) bad mark chip, (2) chip in good shape, and (2) no chip. Note that the above-mentioned bad mark is a mark attached to a wafer chip with abnormal electrical characteristics.

Next, FIG. 5 shows a method for determining whether column #Ft recognition has been completed. As shown in (2) of FIG. It is determined that the row recognition is complete when there are consecutive cases where there are no chips or no chips in the recognition area A, and when there are consecutive cases where there are no four wafer chips in the recognition area A as shown in (lVl). B)
is a flowchart, in which it is determined in step 105 whether two or more wafer chips have defective shapes or no chips in recognition area A, and step 1
At 0B, it is determined whether all four wafer chips are present in the next EFt recognition area, and if both conditions are satisfied, it is determined at step 107 that the row recognition is complete.

In addition, Figure 6 shows a method for determining when all recognition has been completed, and as shown in Figure 6 (a), as shown in "Scream → M", after column recognition has been performed (2), there is a When a state in which all four wafer chips are missing is detected twice in a row, it is determined that all recognition has been completed. In addition, FIG. 6(B) is a flowchart of the process, and in step 108, after the end of row recognition, it is determined whether or not a state in which all four wafer chips in recognition area A are missing is detected twice in a row, and the result is determined. If the result is YES, it is determined in step 109 that all recognition has been completed.

However, since the present invention recognizes multiple wafer chips at the same time, it is easy to detect the characteristics of the edge of the wafer as described above, and the recognition required to complete row recognition and all recognition is easy. The number of times can be reduced, and the influence on the mounting tact can be further reduced.

(Effects of the Invention) As described above, in the present invention, visual iFj RLI can be used to determine the shape of a wafer chip, such as chipping and cracking, detecting a bad mark indicating an electrical defect, and detecting the position information of a good chip. In a wafer chip detection method that performs
In one visual detection, multiple wafer chips are taken into one recognition area at the same time, and =R within the recognition area.
Detects the positional relationship of multiple wafer chips and the pitch between wafer chips based on the AT area center, calculates the recognition position of the next multiple wafer chips, and corrects the recognition position while adjusting the recognition position. Since the detection is performed while moving, (a) it automatically corrects variations in the stretching rate of the wafer chips and the inclination when fixing the wafer ring to the XY child table, making it possible to perform recognition that follows the actual arrangement.
It is possible to eliminate the need for operator intervention as in the conventional case.

(b) Instead of one-chip recognition/one-chip mounting, the number of wafer chips greater than the number of wafer chips to be mounted each time is recognized in advance, so even if defective products occur consecutively, the mounting tact is not disturbed.

(c) Since multiple wafer chips are recognized at the same time, it is easy to detect the characteristics of the wafer edge, and the number of recognitions required to complete row recognition and all recognition can be reduced, reducing the impact on mounting tact. can do.

There are other effects.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a system embodying the wafer chip detection method of the present invention, Fig. 2 is a flowchart showing the recognition and mounting process, Fig. 3 is a diagram showing how the recognition area is set, and Fig. 4 is a diagram showing the setting of the recognition area. The figure shows the positional relationship of each wafer chip within the recognition area, Figure 5 is an explanatory diagram of the method for determining the end of row recognition, Figure 6 is an explanatory diagram of the method for determining the end of all 5 liters, and Figure 7 8 is an explanatory diagram of a wafer chip, FIG. 9 is a flowchart showing the recognition and mounting process in the conventional detection method lζ, FIG. 10 is a diagram showing how the recognition area is set, and FIG. 11 is a column FIG. 12 is an explanatory diagram of a conventional method for determining whether recognition has been completed. FIG. 12 is an explanatory diagram of a conventional method for determining whether all recognition has been completed. 1. ITV camera, 2... recognition device, 3... communication line, 4... die bonder controller, II
, lla, llb, lie, 11+(...
...Wafer chip, 14...Wafer ring, 15.
...XY child table A... snoring group ratio area

Claims (1)

[Claims] In a wafer chip detection method that uses visual recognition to determine the shape of chips, cracks, etc. on wafer chips, detect bad marks that indicate electrical defects, and detect position information of good chips, multiple chips are detected in one visual detection. wafer chips are simultaneously taken into one recognition area, and the positional relationship of the plurality of wafer chips with reference to the recognition area center within the recognition area and the pitch between the wafer chips are detected,
A method for detecting wafer chips characterized by calculating the recognition positions of the next plurality of wafer chips and performing detection by moving the recognition positions while correcting the recognition positions.