JPWO2007013145A1 - Semiconductor integrated circuit - Google Patents

Abstract

In a semiconductor integrated circuit having a plurality of power supply systems, each power supply system having a plurality of power supply terminals and a plurality of power supply lines, a plurality of power supply lines in each power supply system are provided with two stages of bidirectional diode pairs. It connects via a protection circuit (11a, 11b; 12a, 12b; 13a, 13b). Also, between the lines between the two-stage protection circuits of each power supply system, they are connected via a protection circuit (15a, 15b) consisting of a parallel MOSFET and a series diode, corresponding to at least one signal terminal. The protective element (Dd2d1) provided in this manner is connected between the signal terminal and one of the lines between the two-stage protective circuits.

Description

  The present invention relates to a technique for preventing electrostatic breakdown of a semiconductor integrated circuit, and further to a technique that is effective when applied to a semiconductor integrated circuit having two or more power supply systems. In particular, the present invention is used for a semiconductor integrated circuit in which a bipolar transistor circuit and a CMOS circuit are mixedly mounted. Related to effective technology.

  In semiconductor integrated circuits, in order to protect internal elements from external static electricity and surge voltage, the electrostatic breakdown resistance is improved by providing a discharge path that does not pass through the internal circuit that sends current to the power supply terminal through a protective diode. An electrostatic protection circuit is provided.

  FIG. 1 to FIG. 9 show an electrostatic protection circuit studied by the inventor prior to the present invention. The electrostatic protection circuit of FIG. 1 is applied to a semiconductor integrated circuit having two types of power supply systems of Vcc and Vdd and a ground system, and a plurality of power supply terminals provided for each power supply system. In the semiconductor integrated circuit of FIG. 1, two power supply terminals Vcc1 and Vcc2 to which a power supply voltage Vcc of the same level is applied are connected by a line L1, and two protections comprising a pair of bidirectionally connected diodes on the line L1. Circuits 11a and 11b are provided.

  In addition, two power supply terminals Vdd1 and Vdd2 to which the same level of power supply voltage Vdd is applied are connected by a line L2, and two protection circuits 12a and 12b each including a pair of bidirectionally connected diodes are provided on the line L2. It has been. Further, the two ground terminals Gnd1 and Gnd2 to which the ground potential GND is applied are connected by a ground line L3, and two protection circuits 13a and 13b composed of bidirectional parallel-connected diode pairs are provided on the ground line L3. ing.

  Further, the signal terminal S1c1 of the Vcc system circuit is provided with a protection circuit 14a including a diode Dcc1 that is forward directed toward the power supply terminal Vcc1 and a diode Dcg1 that is reversed toward the ground terminal GND1. The signal terminal S1d1 of the Vdd system circuit is provided with a protection circuit 14c including a diode Ddd1 that is forward directed toward the power supply terminal Vdd1 and a diode Ddg1 that is directed backward toward the ground terminal Gnd1. Similarly, a protection circuit 14b composed of diodes Dc2g1 and Dc2c1 is provided at the signal terminal S2c1 of the Vcc system circuit, and a protection circuit 14d composed of diodes Dd2g1 and Dd2d1 is provided at the signal terminal S2d1 of the Vdd system circuit. It has been.

  Further, a different power source protection circuit 15a is provided between the connection node Nesc between the protection circuits 11a and 11b on the line L1 and the connection node Nesd between the protection circuits 12a and 12b on the line L2. Further, a different power source protection circuit 15b is provided between the connection node Nesd between the protection circuits 12a and 12b on the line L2 and the connection node Nesg between the protection circuits 13a and 13b on the line L3.

Among them, the protection circuit 15a between different power sources includes a MOSFET (insulated gate field effect transistor) Mn01 whose gate and source are coupled via a resistor R0n1, and two series diodes Ddc1 and Ddc2 in parallel therewith. It is configured. The different power supply protection circuit 15b includes a MOSFET Mn02 in which a gate and a source are coupled via a resistor Rn2.
Japanese Patent Laid-Open No. 11-289053

  When evaluating the electrostatic breakdown tolerance of a semiconductor integrated circuit, the internal elements must be destroyed when positive static electricity is applied to the signal terminals and negative static electricity is applied to each power supply terminal. It is verified whether or not a discharge current flows. 2 to 7 show a case in which positive static electricity is applied to the signal terminals S1c1 and S1d1 with respect to the power supply terminals Gnd1, Vcc1, and Vdd1 in the semiconductor integrated circuit to which the protection circuit of FIG. When a static electricity is applied, the path of the discharge current when the protection circuit functions normally is shown.

  Further, FIG. 8 shows protection in the case where positive static electricity is applied to the signal terminal S2d2 of another power supply system (Vdd2) with reference to the power supply terminal Vdd1 in the semiconductor integrated circuit to which the protection circuit of FIG. 1 is applied. The path of the discharge current when the circuit functions normally is shown. However, according to the verification by the present inventors, the wiring impedance of the protection circuit as viewed from the reference power supply terminal is increased due to the arrangement relationship between the internal circuit, the protection circuit, and the power supply terminal, and the elements constituting the internal circuit and the protection Depending on the relationship between the constants of the elements, the discharge current may escape through the internal circuit without passing through the assumed discharge current path. FIG. 9 shows an example of such discharge. It has been clarified that such an electric discharge may cause destruction of elements constituting the internal circuit.

  Further, in the conventional electrostatic protection circuit, if the electrostatic breakdown resistance is increased by designing the layout of the internal circuit and the protection circuit, the degree of freedom in design is restricted, and thus a long time is required for the design. At the same time, when electrostatic breakdown is detected after trial manufacture, it is necessary to redo the layout design to avoid this, and there is a problem that the IC development period is extended.

  As an invention related to a conventional electrostatic protection circuit related to the present invention, there is an invention described in Patent Document 1, for example. The prior invention is similar to the present invention in that a protection circuit comprising a bidirectional diode is provided between a power supply voltage terminal for an analog circuit and a power supply voltage terminal for a digital circuit. However, in the prior invention of Patent Document 1, the power supply voltage for the analog circuit and the power supply voltage for the digital circuit are at the same level. Therefore, the present invention in which a protection circuit composed of a bidirectional diode is provided between a plurality of power supply voltages at the same level and a protection circuit is provided between different power supply voltages at different levels is clearly different from the prior invention. The configuration is different.

An object of the present invention is to provide an electrostatic breakdown prevention technique capable of effectively preventing destruction of internal elements due to static electricity or surge voltage in a semiconductor integrated circuit having two or more power supply systems.
Another object of the present invention is to provide a semiconductor integrated circuit technology that can increase the resistance to electrostatic breakdown without restricting the degree of freedom in layout design or extending the layout design period of internal circuits and protection circuits. It is in.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, in a semiconductor integrated circuit having a plurality of power supply systems and each power supply system having a plurality of power supply terminals and a plurality of power supply lines, a space between the plurality of power supply lines of each power supply system is formed of a pair of bidirectional diodes. Connect through stage protection circuit. The lines between the two-stage protection circuits of each power supply system are connected via a protection circuit composed of a parallel MOSFET and a series diode, and are provided corresponding to at least one signal terminal. The element is connected between the signal terminal and one of the lines between the two-stage protection circuits.

  Generally, a protection element provided corresponding to a signal terminal is connected between the signal terminal and a power supply line directly connected to the power supply terminal. The impedance of the seen power supply line may be high, and there is a possibility that a discharge path for releasing static electricity applied to the signal terminal passes through the internal circuit.

  On the other hand, according to the above-described means, the protection element is connected between the signal terminal and one of the lines between the two-stage protection circuits, thereby reducing the impedance of the power supply line viewed from the protection element. Therefore, it is possible to prevent the discharge path for releasing static electricity from passing through the internal circuit and to increase the electrostatic breakdown resistance. In addition, the design change in which the terminal opposite to the signal terminal connection side terminal of the protection element is changed from the power supply line directly connected to the power supply terminal to one of the lines between the two-stage protection circuits is Compared to a design change that changes the layout, this can be done in a short time. Thereby, the development period of the semiconductor integrated circuit can be shortened.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
In other words, according to the present invention, it is possible to realize a semiconductor integrated circuit capable of increasing the electrostatic breakdown resistance without restricting the degree of freedom in layout design or extending the layout design period of the internal circuit or the protection circuit. .

FIG. 1 is a circuit configuration diagram showing an electrostatic protection circuit studied prior to the present invention. FIG. 2 shows the discharge current when the protection circuit functions normally when positive static electricity is applied to the signal terminal S1d1 with respect to the power supply terminal Gnd1 in the electrostatic protection circuit studied prior to the present invention. It is circuit explanatory drawing which shows a path | route. FIG. 3 shows the discharge current when the protection circuit functions normally when negative static electricity is applied to the signal terminal S1d1 with respect to the power supply terminal Gnd1 in the electrostatic protection circuit studied prior to the present invention. It is circuit explanatory drawing which shows a path | route. FIG. 4 shows the discharge current when the protective circuit functions normally when positive static electricity is applied to the signal terminal S1d1 with respect to the power supply terminal Vdd1 in the electrostatic protection circuit studied prior to the present invention. It is circuit explanatory drawing which shows a path | route. FIG. 5 shows the discharge current when the protective circuit functions normally when negative static electricity is applied to the signal terminal S1d1 with respect to the power supply terminal Vdd1 in the electrostatic protection circuit studied prior to the present invention. It is circuit explanatory drawing which shows a path | route. FIG. 6 shows the discharge current when the protective circuit functions normally when positive static electricity is applied to the signal terminal S1d1 with respect to the power supply terminal Vcc1 in the electrostatic protection circuit studied prior to the present invention. It is circuit explanatory drawing which shows a path | route. FIG. 7 shows the discharge current when the protection circuit functions normally when negative static electricity is applied to the signal terminal S1d1 with respect to the power supply terminal Vcc1 in the electrostatic protection circuit studied prior to the present invention. It is circuit explanatory drawing which shows a path | route. FIG. 8 shows the discharge current when the protective circuit functions normally when positive static electricity is applied to the signal terminal S2d1 with respect to the power supply terminal Vdd1 in the electrostatic protection circuit studied prior to the present invention. It is circuit explanatory drawing which shows a path | route. FIG. 9 shows an electrostatic protection circuit studied prior to the present invention. When positive static electricity is applied to the signal terminal S2d1 with respect to the power supply terminal Vdd1, the protection circuit does not function normally and passes through the internal circuit. It is circuit explanatory drawing which shows a mode that the discharge path was formed. FIG. 10 shows a discharge path assumed when positive static electricity is applied to the signal terminal S2d3 with respect to the power supply terminal Vdd3 in the semiconductor integrated circuit including the electrostatic protection circuit examined prior to the present invention. It is circuit explanatory drawing. FIG. 11 is a circuit explanatory diagram showing an example of the electrostatic protection circuit according to the present invention and a discharge path when positive static electricity is applied to the signal terminal S2d1 with reference to the power supply terminal Vdd1. FIG. 12 is a circuit explanatory diagram showing a modified example of the electrostatic protection circuit of the first embodiment and a discharge path when positive static electricity is applied to the signal terminal S2d1 with reference to the power supply terminal Vdd1 in the modified example. It is. FIG. 13 is assumed when a semiconductor integrated circuit including the electrostatic protection circuit of the embodiment of FIG. 11 and a positive static electricity is applied to the signal terminal S2d3 with reference to the power supply terminal Vdd3 in the semiconductor integrated circuit. It is circuit explanatory drawing which shows a discharge path | route. FIG. 14 is assumed when a positive static electricity is applied to the signal terminal S2d3 with reference to the power supply terminal Vdd3 in the configuration of the electrostatic protection circuit according to the second embodiment and the semiconductor integrated circuit to which the electrostatic protection circuit is applied. It is circuit explanatory drawing which shows a discharge path | route. FIG. 15 is a cross-sectional view showing a specific example of the structure of the protection diode constituting the electrostatic protection circuit of the example. FIG. 16 is a cross-sectional view showing a specific example of the structure of a protection MOSFET constituting the protection circuit between different power sources of the embodiment. FIG. 17 is a block diagram showing a configuration example of an analog front-end LSI that is used in a DVD device and processes a signal from an optical pickup as an example of a semiconductor integrated circuit that is suitable for application of the present invention.

Explanation of symbols

11a, 11b Protection circuit between first power supply terminals at the same level 12a, 12b Protection circuit between second power supply terminals at the same level 13a, 13b Protection circuit between a plurality of ground terminals 14a-14d Protection provided at signal terminals Circuits 15a and 15b Protection circuits between different power supply lines 21a and 21b Vcc internal circuit 22a and 22b Vdd internal circuit 100 Semiconductor substrate 111 N-type buried isolation region 112 Lateral isolation region 120 Island region (diode formation region)
121 Anode region 122 Cathode region 130 Gate electrode 141, 142 N-type source / drain region 150 Low-concentration N-type region for gate-source resistance

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 11 shows a semiconductor integrated circuit to which the electrostatic protection circuit according to the present invention is applied. Although not particularly limited, the semiconductor integrated circuit of FIG. 11 includes two types of power supply systems, Vcc and Vdd, and a ground system (GND), and a plurality of power supply terminals are provided for each power supply system. FIG. 11 shows two terminals for each power supply system among the plurality of power supply terminals. That is, Vcc1 and Vcc2 are Vcc power supply terminals, Vdd1 and Vdd2 are Vdd power supply terminals, and Gnd1 and Gnd2 are ground reference power supply terminals. Furthermore, in order to stabilize the ground system, a common ground terminal CGnd and a common ground line CGL are provided.

  In this embodiment, the power supply voltage Vcc is a voltage of a level higher than Vdd (Vcc> Vdd). The two types of power supply systems are provided in this way because a bipolar transistor circuit that operates at a high voltage and a CMOS circuit that operates at a low voltage are provided. When the semiconductor integrated circuit is configured as a circuit in which a bipolar transistor circuit and a CMOS circuit are mixed, a potential such as 5 cc for Vcc and 3.3 V for Vdd is selected. In FIG. 11, 21a and 21b are internal circuits composed of bipolar transistor circuits, and 22a and 22b are internal circuits composed of CMOS circuits. Note that 22a and 22b may be circuits in which bipolar transistors and CMOS are mixed. Each of 21a, 21b, 22a and 22b is also supplied with a ground reference power supply.

  In the semiconductor integrated circuit of this embodiment, two power supply terminals Vcc1 and Vcc2 to which the same level of power supply voltage Vcc is applied are connected by a line L1, and two parallel parallel connection diode pairs are provided on the line L1. Protection circuits 11a and 11b are provided.

  Further, the two power supply terminals Vdd1 and Vdd2 to which the same level of the power supply voltage Vdd is applied are connected by a line L2, and two protection circuits 12a and 12b composed of bidirectional parallel connected diode pairs are provided on the power supply line L2. Is provided. Further, the two ground terminals Gnd1 and Gnd2 to which the ground potential GND is applied are connected by a line L3, and two protection circuits 13a and 13b each including a pair of bidirectionally connected diodes are provided on the line L3. .

  Further, the signal terminal S1c1 of the Vcc system circuit is provided with a protection circuit 14a including a diode Dcc1 that is forward directed toward the line L1 and a diode Dcg1 that is reversed toward the ground terminal Gnd1. The signal terminal S2c1 is provided with a protection circuit 14b including a diode Dc2c1 that is forward directed toward the line L1 and a diode Dc2g1 that is reversed toward the ground terminal Gnd2.

  The signal terminal S1d1 of the Vdd system circuit is provided with a protection circuit 14c composed of a diode Ddd1 that is in the forward direction toward the line L2 and a diode Ddg1 that is in the opposite direction toward the ground terminal Gnd1. The signal terminal S2d1 is provided with a protection circuit 14d including a diode Dd2g1 that is forward directed toward the line L2 and a diode Dd2d1 that is reversed toward the ground terminal Gnd2.

  Further, a different power source protection circuit 15a is provided between the connection node Nesc between the protection circuits 11a and 11b on the line L1 and the connection node Nesd between the protection circuits 12a and 12b on the in L2. Further, a different power source protection circuit 15b is provided between the connection node Nesd between the protection circuits 12a and 12b on the line L2 and the connection node Nesg between the protection circuits 13a and 13b on the line L3.

  Among these, the different power supply protection circuit 15a is composed of a MOSFET Mn01 whose gate and source are coupled via a resistor R0n1 and two series diodes Ddc1 and Ddc2. The different power supply protection circuit 15b includes a MOSFET Mn02 in which a gate and a source are coupled via a resistor R0n2.

  As can be seen from a comparison with FIG. 1 showing the electrostatic protection circuit studied prior to the present invention, the difference between the electrostatic protection circuit of this embodiment and the electrostatic protection circuit of FIG. The cathode terminals of the diodes Dcc1 and Dc2c1 are connected to the power supply line L1 between the protection circuits 11a and 11b, not the power supply terminals Vcc1 and Vcc2. Similarly, the cathode terminals of the diodes Ddd1 and D2d1 constituting the protection circuits 14c and 14d are connected to the line L2 between the protection circuits 12c and 12d instead of the power supply terminals Vdd1 and Vdd2.

  As described above, in the circuit of FIG. 1, when positive static electricity is applied to the signal terminal S2d1 of another power supply system (Vdd2) with reference to the power supply terminal Vdd1, the original discharge path is as shown in FIG. The discharge current may escape through the internal circuit without passing through. On the other hand, in the circuit of FIG. 11, as indicated by the thick line A, the discharge current flows through the discharge path including the line L2 without passing through the internal circuit. The impedance of the discharge path in this embodiment may be lower than the impedance of the discharge path from the signal terminal S2d1 to the power supply terminal Vdd2 and the discharge path passing through the internal circuit in FIG. Therefore, by applying this embodiment, even if the Vdd1 internal circuit 22a and the Vdd2 internal circuit 22b are arranged close to each other as shown in FIG. 12, for example, the discharge is made through the original discharge path. It is possible to avoid electrostatic breakdown of the elements constituting the internal circuit.

  In the MOSFET in which the gates and sources included in the different power supply protection circuits 15a and 15b are coupled via the resistor R0n1, normally, no current flows through the channel. However, as shown in FIG. 5 and FIG. When negative static electricity is applied to the signal terminal S1d1 with respect to Vcc1 or Vdd1, a current flows due to the punch-through effect. As a result, the discharge current can flow without passing through the internal circuit.

  In this embodiment, among the different power supply protection circuits 15a and 15b, diodes Ddc1 and Ddc2 in series only with 15a are provided in parallel with the MOSFET. This is because when a positive static electricity is applied to the signal terminal S1d1 with reference to the power supply terminal Vcc1, the protection element Ddd1, the line L2, the diodes Ddc2, Ddc1, the line L1, the protection circuit 15a between the different power supplies. It is desirable to have Ddc1 and Ddc2 in order to flow a discharge current flowing through the protective element Dec1 to the power supply terminal Vcc1. On the other hand, when positive static electricity is applied to the signal terminal S1d1 with respect to the power supply terminal Vdd1, the signal terminal This is because there is a discharge path that does not pass through the different power supply protection circuit 15b because the discharge path flows from S1d1 to the power supply terminal Vdd1 through the protection element Ddd1, the line L2, and the protection element Ded1. Even if a discharge path that flows from the line L3 to the line L2 is created, when configuring a Vdd internal circuit composed of CMOS, the NMOS Pwell is connected to the GND from the GND power supply line, and the PMOS Nwell is connected to the Vdd. Since it is biased to Vdd from the system power supply line, a large number of one-stage diodes whose forward direction is from L3 to L2 are formed. For example, since this area occupies nearly 10% of the entire chip, it is not necessary to provide a diode in parallel with the protection circuit 15b between different power sources. The reason why not only one diode but two diodes are provided in series in the different power supply protection circuit 15a is that the reverse withstand voltage is small with only one diode, and current flows through the discharge path as shown in FIG. This is because the diode may be destroyed.

  FIG. 13 shows an example of the layout of the entire semiconductor integrated circuit to which the embodiment of FIG. 11 is applied. In FIG. 13, the same circuits and elements as those in FIG.

  In the semiconductor integrated circuit of FIG. 13, along each side of the chip, a line L1 for connecting Vcc power supply lines for supplying the power supply voltage Vcc to the internal circuit via two bidirectional diodes, and the internal circuit Lines L2 for connecting the Vdd power supply lines for supplying the power supply voltage Vdd to each other via two bidirectional diodes are arranged in a loop (loop). A different power supply protection circuit 15a is provided between the lines L1 and L2, and a different power supply protection circuit 15b is provided between the line L2 and the ground point (ground line). In FIG. 13, the lines L3 and CGL (GND) are not shown, but they are arranged in a ring shape like the lines L1 (Vcc) and L2 (Vdd).

  For comparison, FIG. 10 shows an example of the layout of the entire semiconductor integrated circuit to which the study technique of FIG. 1 is applied. Further, in FIG. 10 and FIG. 13, the discharge path assumed in the design stage is indicated by a bold line when positive static electricity is applied to the signal terminal S2d3 with reference to the power supply terminal Vdd3.

  In the semiconductor integrated circuit to which the study technique of FIG. 1 is applied, as shown in FIG. 10, the assumed discharge path is a redundant path that is considerably detoured. Therefore, the impedance of the assumed discharge path becomes high, and there is a possibility that the discharge path is generated through the internal circuit. On the other hand, in the semiconductor integrated circuit of FIG. 13 to which the embodiment of FIG. 11 is applied, the assumed discharge path is considerably shortened as shown by the thick line in FIG. Therefore, the impedance of the assumed discharge path is lowered, and there is little possibility that the discharge path is generated through the internal circuit, and the electrostatic breakdown resistance is improved.

FIG. 14 shows the overall layout of another embodiment of the semiconductor integrated circuit to which the present invention is applied.
In FIG. 14, the same circuits and elements as those in FIG. The difference between FIG. 14 and FIG. 13 is as follows. In FIG. 13, the cathodes of the protection diodes 14a to 14e of the signal terminals S1d1, S1d2, S1d3... S4d1, S4d1, S4d2, and S4d3 for the Vdd internal circuit are all connected to the line L2 (Vdd). . On the other hand, in FIG. 14, only the protection diode Dd2d3 of the protection circuit 14e of the signal terminal S2d3 has the cathode connected to the line L2 (Vdd), and the cathodes of the other protection diodes are connected to the power supply line Lvd directly connected to the power supply terminal Vdd2. Yes.

  Like this embodiment, the cathode of the protection diode of the protection circuit 14 of the signal terminal for the Vdd internal circuit is connected to the Vdd power supply line Lvd according to the impedance of the discharge path, and the line L2 between the protection circuits In some cases, it is possible to improve the electrostatic breakdown resistance of all signal terminals by separating them into those to be connected. Whether the cathode of one protection diode of the Vcc internal circuit signal terminal protection circuit is connected to the line L1 or to the power supply line directly connected to the power supply terminal Vcc in accordance with the characteristics of the product to be manufactured. It may be changed, and it may be changed whether the cathode of one protection diode of the protection circuit for the Vdd system internal circuit signal terminal is connected to the line L2 or to the power supply line directly connected to the power supply terminal Vdd.

  As described above, in the above embodiment, the impedance of the power supply line viewed from the protection element is lowered by connecting the protection element between the signal terminal and one of the lines between the two-stage protection circuits. Therefore, it is possible to avoid a discharge path for discharging static electricity through the internal circuit, and to increase the electrostatic breakdown resistance.

  In addition, the design change in which the terminal opposite to the signal terminal connection side terminal of the protection element is changed from the power supply line directly connected to the power supply terminal to one of the lines between the two-stage protection circuits is Compared to a design change that changes the layout, this can be done in a short time. Thereby, the development period of the semiconductor integrated circuit can be shortened. In other words, there is an effect that it is possible to realize a semiconductor integrated circuit capable of increasing the electrostatic breakdown resistance without restricting the degree of freedom of layout design or extending the layout design period of the internal circuit or the protection circuit. .

FIG. 15 shows a specific example of the structure of the protection diode constituting the protection circuits 11a, 11b, 12a, 12b, 13a, 13b, and 15a of the embodiment.
The protection diode of this embodiment includes an N-type buried isolation region 111 formed in a semiconductor substrate 100 such as P-type single crystal silicon, and a lateral isolation region formed in a frame shape so as to reach the isolation region 111. It is formed in an island region 120 surrounded by 112. This island region 120 is constituted by a layer (hereinafter referred to as an epi layer Epi) 110 epitaxially grown on the semiconductor substrate 100, and the lateral isolation region 112 is a P type in which an N channel MOSFET of a CMOS circuit (not shown) is formed. The surface side is formed as a P-type region P-WELL by being formed at the same time as the well region forming step.

  On the surface of the island region 120, a P-type region 121 serving as an anode region of the protection diode and an N-type region 122 serving as a cathode region are formed at a slight distance. The N-type region 122 serving as the cathode region is formed to be deeper than the N-type region serving as the N channel MOSFET source / drain region of the CMOS circuit (not shown). As a result, the current density is reduced to prevent the element from being deteriorated or destroyed when a discharge current flows.

  A P-type buried isolation region 113 is formed below the P-type region P-WELL. The outside of the lateral isolation region 112 is also a P-type region P-WELL formed at the same time in the same process as the P-type well region. The lateral isolation region 112 itself is formed as an N-type region N-WELL by being simultaneously formed in the same process as the process of forming an N-type well region in which a P-channel MOSFET of a CMOS circuit (not shown) is formed.

  Further, the N-type well region of the lateral isolation region 112 and the buried isolation region 111 are simultaneously formed in the same process as the process of forming a buried collector region of a vertical bipolar transistor (not shown), thereby forming an N-type. The region is NBL. In the protection diode of this embodiment, a conductive layer serving as a wiring is formed so that the same potential as that of the P-type region 121 serving as an anode region is applied to the lateral isolation region 112. This lateral isolation region 112 is transmitted to the potential N-type buried isolation region 111 and is reverse-biased with the P-type substrate 100.

  According to the diode having the structure as shown in FIG. 15, the P-type region 121 as the anode region and the N-type buried isolation region 111 are always at the same potential. Therefore, even if a parasitic PNP bipolar transistor exists between the P-type region 120 as the diode formation region, the N-type buried isolation region 111, and the P-type substrate 100, it is not turned on. There is an advantage that no leak current flows or latch-up occurs.

FIG. 16 shows an embodiment of the structure of the gate-source coupling protection MOSFET constituting the protection circuits 15a and 15b of the above-described embodiment.
In the protection MOSFET of this embodiment, a gate electrode 130 is formed on the surface of the epi layer 110 on the semiconductor substrate via a gate insulating film, and a relatively deep N-type source is formed on the epi layer surface on both sides of the gate electrode 130. -Drain regions 141 and 142 are formed. For example, the N-type regions 141 and 142 are formed in the same process as the N-type region serving as a collector outlet of a general vertical bipolar transistor (not shown), thereby simplifying the manufacturing process. At the same time, the N-type regions 141 and 142 are made deeper than the source / drain regions of a normal MOSFET constituting a CMOS circuit (not shown), thereby reducing the current density when a discharge current flows and reducing the element density. Deterioration is prevented.

  In FIG. 16, 150 is a low-concentration N-type region that serves as a gate-source resistance of the protection MOSFET, and 151 and 152 are high-concentration regions as contact regions with electrodes formed at both ends of the N-type region 150. It is an N-type region. The low-concentration N-type region 150 is manufactured by the same process as the base diffusion region of the bipolar transistor (not shown), and the high-concentration N-type regions 151 and 152 are formed by the same process as the emitter region of the bipolar transistor (not shown). The process is simplified.

  The N-type source / drain regions 141 and 142 of the protection MOSFET may not be the same process as the N-type region that becomes the collector outlet of the bipolar transistor. However, even in that case, the N-type source / drain regions 141 and 142 can be formed in the same process as the N-type region 122 as the cathode region of the protection diode in FIG. 15, thereby increasing the number of manufacturing processes. Can be suppressed.

  FIG. 17 shows a configuration example of an analog front-end LSI that processes a signal from an optical pickup and a DVD apparatus using the analog front-end LSI as an example of a semiconductor integrated circuit that is suitable for application of the present invention.

  The analog front end LSI 200 includes an interface circuit 210 having a level shift circuit that converts a signal input from the photoelectric conversion circuit of the optical pickup into a signal of a level suitable for a circuit inside the LSI. The analog front-end LSI also includes an RF system circuit 220 that performs processing such as detecting an envelope of a high-frequency signal input from the pickup, wobble extraction and ID area detection for detecting a recording position (address). And a second detection circuit 240 for detecting MIRR, Defect, and the like. Further, the analog front-end LSI includes a servo system circuit 250 that processes a signal from the pickup for alignment in a focus direction, a tracking direction, and the like, an OPC circuit 260 that performs signal extraction for verifying recording quality, An automatic power control circuit 270 that controls the output and a register 280 that holds a set value from the higher-level control LSI 300 are provided.

  Among the circuit blocks, for example, a level shift circuit that operates with a Vcc power supply and a Vdd power supply is provided in a previous stage of the interface circuit 210. Further, an analog circuit composed of a bipolar transistor that operates with a Vcc power supply may be used for the amplifier of the RF system circuit 220, the servo system circuit 250, the automatic power control circuit 270, and the like. On the other hand, from the viewpoint of reducing power consumption, the register 280 and the like are preferably formed of a digital circuit formed of a CMOS circuit. The analog / digital mixed analog front-end LSI 200 is an effective semiconductor integrated circuit configured to operate with two power supplies, and a desirable result can be obtained by applying the electrostatic protection circuit of the above embodiment to this.

  The optical pickup 400 includes an LD driver 410 that drives a light emitting element that irradiates an optical disk with laser light, and a front monitor detector 420 that detects light emission intensity in order to make the light amount of the light emitting element constant. The optical pickup 400 also includes a photoelectric conversion IC 430 that converts reflected light from the optical disk into an electrical signal and amplifies it, an actuator 440 that aligns the focus direction, the tracking direction, and the like.

  The control LSI 300 includes an AD conversion circuit 310 that AD converts a signal from the analog front end LSI 200, and a central processing unit (CPU) 320 that performs processing such as generation of a servo control signal according to a program. The control LSI 300 also has functions for performing data decoding, encoding (compression), error correction, decoding (decompression), and the like. Note that the control LSI 300 and the analog front end LSI 200 may be formed on a single semiconductor substrate, or may be an IC (SIP) mounted in one package.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, the application to a semiconductor integrated circuit having two types of power supply systems of Vcc and Vdd has been described. However, the present invention can be applied to a semiconductor integrated circuit having three types of power supply systems.

  In the above description, the invention mainly applied to the so-called BiCMOS semiconductor integrated circuit in which a bipolar transistor circuit and a CMOS circuit are mixedly used has been described. The present invention is not limited to this, and can be generally used for a semiconductor integrated circuit having two or more power supply systems such as a semiconductor integrated circuit composed of only a CMOS circuit.

Claims (21)

From a first power supply terminal to which a power supply voltage of the first power supply system is applied from the outside, a first power supply line for supplying the power supply voltage of the first power supply system to an internal circuit, and from a power supply voltage of the first power supply system from the outside A second power supply terminal to which a power supply voltage of the second power supply system of a lower level is applied, a second power supply line for supplying the power supply voltage of the second power supply system to the internal circuit, and a power supply for the second power supply system from the outside A ground power supply terminal to which a reference power supply voltage of a level lower than the voltage is applied; a ground power supply line that supplies the reference power supply voltage applied to the ground power supply terminal to the internal circuit; and a plurality of signals A semiconductor integrated circuit comprising a terminal,
The second power supply system includes a plurality of second power supply terminals and a plurality of second power supply lines, and the plurality of second power supply lines includes two first protection circuits including a bidirectional diode pair in parallel form, Connected via an intermediate line connecting the first protection circuits,
The intermediate line and the first power supply line are connected via a second protection circuit,
The intermediate line and the ground power line are connected via a third protection circuit,
The plurality of signal terminals include a first protection element connected between the corresponding signal terminal and the intermediate line, and a second protection element connected between the corresponding signal terminal and the ground power line. A semiconductor integrated circuit provided with a fourth protection circuit including the protection element.   The second protection circuit includes an insulated gate field effect transistor in which a source or drain terminal connected to the power supply line and a gate terminal are connected, and a drain or source terminal connected to the first power supply line, and the transistor 2. The semiconductor integrated circuit according to claim 1, further comprising two series-shaped diodes provided in parallel with each other and in a forward direction toward the power supply voltage of the first power supply system.   The third protection circuit includes a second insulated gate field effect transistor in which a source or drain terminal connected to the ground power line is connected to a gate terminal, and a drain or source terminal is connected to the intermediate line. The semiconductor integrated circuit according to claim 2, comprising:   4. The semiconductor integrated circuit according to claim 3, wherein the source or drain terminal and the gate terminal of the insulated gate field effect transistor and the second insulated gate field effect transistor are connected via a resistor.   The first protection element of the fourth protection circuit is a diode connected in a forward direction from the signal terminal toward the intermediate line, and the second protection element is connected to the ground power supply line. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a diode connected in a forward direction toward the signal terminal.   The semiconductor integrated circuit according to claim 1, wherein the intermediate line is provided in a loop shape.   A first internal circuit of a first power supply system that operates by a power supply voltage applied to the first power supply terminal; and a second internal circuit of a second power supply system that operates by a power supply voltage applied to the second power supply terminal. 2. The semiconductor integrated circuit according to claim 1, wherein the reference power supply voltage is supplied to the first internal circuit and the second internal circuit from the ground power supply line.   The semiconductor integrated circuit according to claim 7, wherein the first internal circuit is an analog circuit, and the second internal circuit is a digital circuit.   8. The semiconductor integrated circuit according to claim 7, wherein the first internal circuit is a circuit configured by a bipolar transistor, and the second internal circuit is a circuit configured by an insulated gate field effect transistor.   The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is an analog front-end semiconductor integrated circuit constituting an optical disk device, and a signal supplied from an optical pickup is input to any of the plurality of signal terminals. From a first power supply terminal to which a power supply voltage of the first power supply system is applied from the outside, a first power supply line for supplying the power supply voltage of the first power supply system to an internal circuit, and from a power supply voltage of the first power supply system from the outside A second power supply terminal to which a power supply voltage of the second power supply system of a lower level is applied, a second power supply line for supplying the power supply voltage of the second power supply system to the internal circuit, and a power supply for the second power supply system from the outside A ground power supply terminal to which a reference power supply voltage level lower than the voltage is applied; a ground power supply line for supplying the reference power supply voltage applied to the ground power supply terminal to the internal circuit; and a plurality of signals A semiconductor integrated circuit comprising a terminal,
The first power supply system includes a plurality of first power supply terminals and a plurality of first power supply lines, and the plurality of first power supply lines include two first protection circuits including bidirectional diode pairs in parallel form, Connected via a first intermediate line connecting the first protection circuits,
The second power supply system includes a plurality of second power supply terminals and a plurality of second power supply lines, and the plurality of second power supply lines includes two first protection circuits including a bidirectional diode pair in parallel form, Connected via a second intermediate line connecting the first protection circuits,
The ground system includes a plurality of ground terminals and a plurality of ground lines, and the plurality of ground lines connect two first protection circuits including a pair of bidirectional diodes in parallel with each other. Connected through the third intermediate line,
The first intermediate line and the second intermediate line are connected via a second protection circuit,
The second intermediate line and the third intermediate line are connected via a third protection circuit,
The plurality of signal terminals include a first protection element connected between the corresponding signal terminal and the first or second intermediate line, and a connection between the corresponding signal terminal and one of the ground lines. A semiconductor integrated circuit provided with a fourth protection circuit including the second protection element formed.   The second protection circuit includes an insulated gate field effect transistor in which a source or drain terminal connected to the second intermediate line and a gate terminal are connected, and a drain or source terminal is connected to the first power line, 12. The semiconductor integrated circuit according to claim 11, further comprising two series-shaped diodes provided in parallel with the transistor and directed in the forward direction toward the power supply voltage of the first power supply system.   The third protection circuit includes a second insulated gate field effect in which a source or drain terminal connected to the third intermediate line and a gate terminal are connected, and a drain or source terminal is connected to the second intermediate line. 13. The semiconductor integrated circuit according to claim 12, comprising a transistor.   14. The semiconductor integrated circuit according to claim 13, wherein in the insulated gate field effect transistor and the second insulated gate field effect transistor, the source or drain terminal and the gate terminal are connected via a resistor.   The first protection element of the fourth protection circuit is a diode connected in a forward direction from the signal terminal toward the first or second intermediate line, and the second protection element is any one of the above The semiconductor integrated circuit according to claim 11, wherein the semiconductor integrated circuit is a diode connected in a forward direction from the ground line toward the signal terminal.   The semiconductor integrated circuit according to claim 11, wherein the intermediate line is provided in a loop shape.   A first internal circuit of a first power supply system that operates by a power supply voltage applied to the first power supply terminal; and a second internal circuit of a second power supply system that operates by a power supply voltage applied to the second power supply terminal. The first internal circuit and the second internal circuit are supplied with the reference power supply voltage from the ground line, and the first protective element of the signal terminal that supplies a signal to the first internal circuit is the signal terminal. The second protection element is connected so as to be forward from one of the ground lines to the signal terminal. The diode is a diode connected to the first protection element of the signal terminal for supplying a signal to the second internal circuit in a forward direction from the signal terminal toward the second power supply line. A de, the second protection element semiconductor integrated circuit according to claim 11 which is a diode connected such that the forward direction toward the signal terminal from the one of the ground lines.   The semiconductor integrated circuit according to claim 17, wherein the first internal circuit is an analog circuit, and the second internal circuit is a digital circuit.   The semiconductor integrated circuit according to claim 17, wherein the first internal circuit is a circuit configured by a bipolar transistor, and the second internal circuit is a circuit configured by an insulated gate field effect transistor.   12. The semiconductor integrated circuit according to claim 11, wherein the semiconductor integrated circuit is an analog front-end semiconductor integrated circuit constituting an optical disk device, and a signal supplied from an optical pickup is input to any of the plurality of signal terminals.   And a third protection element connected between the signal pin and the first power supply line or the second power supply line, and one of the signal pin and the ground line. The semiconductor integrated circuit according to claim 11, further comprising a fourth protection circuit including a fourth protection element connected between the first and second protection elements.

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