JPWO2006123467A1 - Electronic components - Google Patents

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JPWO2006123467A1
JPWO2006123467A1 JP2007516213A JP2007516213A JPWO2006123467A1 JP WO2006123467 A1 JPWO2006123467 A1 JP WO2006123467A1 JP 2007516213 A JP2007516213 A JP 2007516213A JP 2007516213 A JP2007516213 A JP 2007516213A JP WO2006123467 A1 JPWO2006123467 A1 JP WO2006123467A1
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conductor pattern
shrinkage
electronic component
insulating layer
layers
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JP4535126B2 (en
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和彦 山野
和彦 山野
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F17/0013Printed inductances with stacked layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041Printed circuit coils
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/28Coils; Windings; Conductive connections
    • H01F27/30Fastening or clamping coils, windings, or parts thereof together; Fastening or mounting coils or windings on core, casing, or other support
    • H01F27/306Fastening or mounting coils or windings on core, casing or other support

Abstract

従来の電子部品は、いずれも細長い導体パターンに形成された幅の広い部分(楔形状部を含む)有するが、これらの幅広の部分は電流が集中して隣接する導体パターンとの間で短絡しやすい。また、幅広の部分を導体パターンの中間に有する場合には焼成時に導体パターンの収縮によるセラミックグリーンシートからの位置ズレを防止することが難しく、上下の導体パターン間に位置ズレが生じ、電気的特性が劣化する。本発明の電子部品10は、絶縁層111〜114が積層された積層体11と、この積層体11内に形成された導体パターン層121〜124と、を備え、導体パターン層121〜124は、複数個所にコーナー部を有し、各コーナー部それぞれに絶縁層111〜114内に食い込む第1収縮ズレ防止部16Aを一体的に設け、且つ、各第1収縮ズレ防止部16Aは各コーナー部の領域内にそれぞれ形成されている。All conventional electronic components have wide portions (including wedge-shaped portions) formed in an elongated conductor pattern, but these wide portions concentrate current and short-circuit between adjacent conductor patterns. Cheap. In addition, when having a wide part in the middle of the conductor pattern, it is difficult to prevent displacement from the ceramic green sheet due to the shrinkage of the conductor pattern during firing, resulting in displacement between the upper and lower conductor patterns, and electrical characteristics Deteriorates. The electronic component 10 of the present invention includes a laminate 11 in which insulating layers 111 to 114 are laminated, and conductor pattern layers 121 to 124 formed in the laminate 11, and the conductor pattern layers 121 to 124 include: There are corner portions at a plurality of locations, and each corner portion is integrally provided with a first shrinkage prevention portion 16A that bites into the insulating layers 111 to 114, and each first shrinkage prevention portion 16A is provided at each corner portion. Each is formed in a region.

Description

本発明は、携帯電話、電子機器等に使用されるインダクタ等の電子部品に関し、更に詳しくは、電気的特性に優れた電子部品に関するものである。   The present invention relates to an electronic component such as an inductor used in a mobile phone, an electronic device, and the like, and more particularly to an electronic component having excellent electrical characteristics.

この種の電子部品としては、例えば特許文献1に記載のインダクタがある。この技術はリソグラフィ法を用いてインダクタを製造する方法に関する。即ち、この技術では、例えばPETフィルムをベース基材とし、ベース基材上に感光性絶縁ペーストを印刷、露光、現像し、更に必要に応じて露光した後、乾燥して絶縁層を形成する。この絶縁層上に感光性電極ペーストを印刷、露光し、現像し、乾燥してコイル状の電極パターンを形成する。次いで、電極パターンの上面に感光性絶縁ペーストを印刷、露光、現像し、更に必要に応じて露光した後、乾燥して絶縁層及びビアホールを形成する。以降、電極パターン、ビアホールを有する絶縁層を交互に積層して生の積層体が形成されている。   An example of this type of electronic component is an inductor described in Patent Document 1. This technique relates to a method of manufacturing an inductor using a lithography method. That is, in this technique, for example, a PET film is used as a base substrate, and a photosensitive insulating paste is printed, exposed and developed on the base substrate, further exposed as necessary, and then dried to form an insulating layer. A photosensitive electrode paste is printed on this insulating layer, exposed, developed, and dried to form a coiled electrode pattern. Next, a photosensitive insulating paste is printed, exposed and developed on the upper surface of the electrode pattern, further exposed as necessary, and then dried to form an insulating layer and a via hole. Thereafter, a raw laminate is formed by alternately laminating electrode layers and insulating layers having via holes.

ベース基材を生の積層体から剥離すると、例えば図6の(a)に示す生の積層体1Aが得られる。この積層体1Aは、同図に示すように、絶縁層2Aと、絶縁層2Aの上面に形成されたコイル状の電極パターン3Aとが交互に繰り返して積層して形成され、上下の電極パターン3A、3Aがビア導体4Aを介して電気的に接続されている。そして、最下層の絶縁層2A上には最下層の電極パターン3Aの引き出し電極部5Aが積層体1Aの左端面から露出し、上から二番目の絶縁層2A上には最上層の電極パターン3Aの引き出し電極6Aが積層体1Aの右端面から露出している。尚、図6の(a)、(b)はインダクタ1個分を示しているが、実際の積層体は複数のインダクタが一括して形成された集合体として得られる。   When the base substrate is peeled from the raw laminate, for example, a raw laminate 1A shown in FIG. 6 (a) is obtained. As shown in the figure, the laminate 1A is formed by alternately and repeatedly laminating insulating layers 2A and coiled electrode patterns 3A formed on the upper surface of the insulating layer 2A. 3A is electrically connected via the via conductor 4A. The lead electrode portion 5A of the lowermost electrode pattern 3A is exposed from the left end surface of the multilayer body 1A on the lowermost insulating layer 2A, and the uppermost electrode pattern 3A is exposed on the second insulating layer 2A from the top. The lead electrode 6A is exposed from the right end surface of the multilayer body 1A. 6A and 6B show one inductor, an actual laminated body is obtained as an aggregate in which a plurality of inductors are collectively formed.

然る後、生の積層体の集合体を所定の温度で焼成した後、個々の積層体に切断し、図6の(b)に示す個々の積層体1を作製する。その後、個々の積層体1に外部電極を設けることにより、高インダクタンス化及び低直流抵抗化された小型のインダクタを得ることができる。   Thereafter, an aggregate of raw laminates is fired at a predetermined temperature, and then cut into individual laminates to produce individual laminates 1 shown in FIG. 6 (b). Thereafter, by providing external electrodes on the individual laminates 1, a small inductor with high inductance and low DC resistance can be obtained.

しかしながら、上述のインダクタの製造方法では、焼成時に絶縁層2Aと電極パターン3Aとの間に収縮挙動に差があるため、図6の(b)に示すように、焼成後に上下の電極パターン3、3間で一点鎖線の基準位置から位置ズレを生じ、絶縁層2A、2A間の層間容量や電極パターン3による電磁界分布が設計値からズレてしまい、インダクタとしての電気的特性が劣化する。   However, in the above-described inductor manufacturing method, since there is a difference in shrinkage behavior between the insulating layer 2A and the electrode pattern 3A at the time of firing, as shown in FIG. A positional deviation occurs from the reference position of the alternate long and short dash line between the three, the interlayer capacitance between the insulating layers 2A and 2A and the electromagnetic field distribution due to the electrode pattern 3 are deviated from the design values, and the electrical characteristics as an inductor deteriorate.

また、焼成時の電極パターン3Aは絶縁層2Aとの収縮挙動の差が大きいため、焼成時に電極パターン3Aが切断し、あるいは電極パターン3Aの引き出し電極5A、6Aが絶縁層2Aの端面から内側へ引っ込み、焼成後の引き出し電極5、6が積層体1の端面に露出せず、外部電極との電気的接続を確保することができず、不良率が増大する虞がある。   Further, since the electrode pattern 3A during firing has a large difference in shrinkage behavior from the insulating layer 2A, the electrode pattern 3A is cut during firing, or the extraction electrodes 5A and 6A of the electrode pattern 3A are inward from the end face of the insulating layer 2A. The lead-out electrodes 5 and 6 after being retracted and fired are not exposed at the end face of the laminated body 1, and electrical connection with the external electrodes cannot be ensured, which may increase the defect rate.

焼成による断線を防止する技術として、例えば特許文献2に記載の技術が知られている。この技術は、インダクタ用の細長い導体パターンに中間部に幅の広い部分、厚みの大きい部分を形成して、導体ペーストの塗布量を多くしておき、焼成によって収縮しても塗布量の多い部分から導体ペーストを補充して導体部分の密度を保てるようにしている。   As a technique for preventing disconnection due to firing, for example, a technique described in Patent Document 2 is known. In this technology, a wide and thick part is formed in the middle part of an elongated conductor pattern for inductors to increase the amount of conductor paste applied, and a part where the amount of application is large even when shrinking by firing. The conductor paste is replenished to maintain the density of the conductor portion.

また、特許文献3では、特許文献2に記載の技術と類似した技術が提案されている。この技術は、導体パターンの端部に楔形状部を設ける技術である。導体パターンの端部に楔形状部を設けることにより、焼結の過程での導体パターンの収縮を抑制し、収縮による導体の接続不良、特に磁性シート端部に導体を確実に露出するようにして、外部電極との接続不良を減少させている。   In Patent Document 3, a technique similar to the technique described in Patent Document 2 is proposed. This technique is a technique in which a wedge-shaped portion is provided at an end portion of a conductor pattern. By providing a wedge-shaped part at the end of the conductor pattern, the shrinkage of the conductor pattern during the sintering process is suppressed, and the conductor is poorly connected due to the shrinkage, in particular, the conductor is reliably exposed at the end of the magnetic sheet. The connection failure with the external electrode is reduced.

特開2003−339660JP 2003-339660 A 特開平11−288831JP-A-11-288831 特開平11−016731Japanese Patent Laid-Open No. 11-016731

しかしながら、特許文献2、3に記載の従来の技術は、いずれも細長い導体パターンに形成された幅の広い部分(楔形状部を含む)によって導体パターンの断線や収縮等の問題を解決することができるが、これらの導体パターンは幅広の部分を有するため、幅広の部分に電流が集中して隣接する導体パターンとの間で短絡しやすく、しかも隣接する導体パターンとの間を詰めるにも限界がある。また、幅広の部分を導体パターンの中間に設ける場合には焼成時に導体パターンの収縮によるセラミックグリーンシートからの端部の位置ズレを防止することが難しく、上下の導体パターン間の収縮が不均一になり、上下の導体パターン間に位置ズレが生じ、電気的特性が劣化する。このことは幅広の部分を導体パターンの端部に設ける場合について同様である。   However, the conventional techniques described in Patent Documents 2 and 3 can solve problems such as disconnection and contraction of the conductor pattern by a wide portion (including the wedge-shaped portion) formed in the elongated conductor pattern. However, since these conductor patterns have a wide portion, current is concentrated on the wide portion, and it is easy to short-circuit between adjacent conductor patterns, and there is a limit to packing between adjacent conductor patterns. is there. In addition, when a wide part is provided in the middle of the conductor pattern, it is difficult to prevent the positional deviation of the end from the ceramic green sheet due to the contraction of the conductor pattern during firing, and the contraction between the upper and lower conductor patterns is uneven. Thus, positional deviation occurs between the upper and lower conductor patterns, and the electrical characteristics deteriorate. This is the same when the wide portion is provided at the end of the conductor pattern.

本発明は、上記課題を解決するためになされたもので、電気的特性に優れ、外部電極との接続信頼性の高い電子部品を提供することを目的としている。   The present invention has been made in order to solve the above-described problems, and an object thereof is to provide an electronic component having excellent electrical characteristics and high connection reliability with an external electrode.

本発明の請求項1に記載の電子部品は、絶縁層が複数積層された積層体と、この積層体内に形成された少なくとも一つの導体パターン層と、を備え、上記導体パターン層は、複数個所に曲折部を有する電子部品であって、上記各曲折部それぞれに上記絶縁層内に食い込む第1収縮ズレ防止部を一体的に設け、且つ、上記各第1収縮ズレ防止部は上記各曲折部の領域内にそれぞれ形成されてなることを特徴とするものである。   The electronic component according to claim 1 of the present invention includes a laminate in which a plurality of insulating layers are laminated, and at least one conductor pattern layer formed in the laminate, and the conductor pattern layer includes a plurality of locations. Each of the bent portions is integrally provided with a first shrinkage prevention portion that bites into the insulating layer, and each of the first shrinkage prevention portions is the bent portion. It is characterized by being formed in each of the regions.

また、本発明の請求項2に記載の電子部品は、請求項1に記載の発明において、上記第1収縮ズレ防止部は、絶縁層の厚さ方向の途中まで形成されてなることを特徴とするものである。   According to a second aspect of the present invention, in the electronic component according to the first aspect, the first shrinkage prevention portion is formed partway in the thickness direction of the insulating layer. To do.

また、本発明の請求項3に記載の電子部品は、請求項1または請求項2に記載の発明において、上記導体パターン層から延設された引き出し電極部を有し、上記引き出し電極部に上記絶縁層内に食い込む第2収縮ズレ防止部を一体的に設け、且つ、上記第2収縮ズレ防止部は上記引き出し電極部の領域内に形成されてなることを特徴とするものである。   An electronic component according to a third aspect of the present invention is the electronic component according to the first or second aspect, further comprising an extraction electrode portion extending from the conductor pattern layer, wherein the extraction electrode portion includes the extraction electrode portion. A second shrinkage-preventing portion that bites into the insulating layer is integrally provided, and the second shrinkage-preventing portion is formed in the region of the extraction electrode portion.

また、本発明の請求項4に記載の電子部品は、請求項3に記載の発明において、上記第2収縮ズレ防止部は、絶縁層の厚さ方向の途中まで形成されてなることを特徴とするものである。   According to a fourth aspect of the present invention, in the electronic component according to the third aspect, the second shrinkage-preventing portion is formed partway in the thickness direction of the insulating layer. To do.

また、本発明の請求項5に記載の電子部品は、請求項1〜請求項4のいずれか1項に記載の発明において、上記導体パターン層が上記絶縁層を介して上下方向に複数形成され、且つ、上下の上記導体パターン層がビア導体によって互いに電気的に接続されてなることを特徴とするものである。   According to a fifth aspect of the present invention, in the electronic component according to any one of the first to fourth aspects, a plurality of the conductor pattern layers are formed in the vertical direction via the insulating layer. The upper and lower conductor pattern layers are electrically connected to each other by via conductors.

本発明の請求項1〜請求項5に記載の発明によれば、電気的特性に優れ、外部電極との接続信頼性の高い電子部品を提供することができる。   According to the first to fifth aspects of the present invention, it is possible to provide an electronic component that has excellent electrical characteristics and high connection reliability with an external electrode.

(a)、(b)はそれぞれ本発明の電子部品の一実施形態を示す図で、(a)はその斜視図、(b)はその内部構造を示す透視図である。(A), (b) is a figure which shows one Embodiment of the electronic component of this invention, (a) is the perspective view, (b) is a perspective view which shows the internal structure, respectively. 図1に示す電子部品を示す分解斜視図である。It is a disassembled perspective view which shows the electronic component shown in FIG. (a)〜(c)はそれぞれ図1に示す電子部品の一部を取り出して示す図で、(a)はその平面図、(b)は(a)のB−B線方向の断面図、(c)は(a)のC−C線方向の断面図である。(A)-(c) is a figure which takes out and shows a part of electronic component shown in FIG. 1, respectively, (a) is the top view, (b) is sectional drawing of the BB line direction of (a), (C) is sectional drawing of the CC line direction of (a). (a)〜(e)はそれぞれ図1に示す電子部品の製造工程の一部を説明するための工程図である。(A)-(e) is process drawing for demonstrating a part of manufacturing process of the electronic component shown in FIG. 1, respectively. (a)、(b)はそれぞれ図1に示す電子部品の主体である積層体を示す図で、(a)は焼成前の生の積層体を示す断面図、(b)は焼成後の積層体を示す断面図である。(A), (b) is a figure which shows the laminated body which is the main body of the electronic component shown in FIG. 1, respectively, (a) is sectional drawing which shows the raw laminated body before baking, (b) is the laminated | stacked after baking. It is sectional drawing which shows a body. (a)、(b)はそれぞれ従来の電子部品の主体である積層体を示す図で、(a)は焼成前の生の積層体を示す断面図、(b)は焼成後の積層体を示す断面図である。(A), (b) is a figure which shows the laminated body which is the main body of the conventional electronic component, respectively, (a) is sectional drawing which shows the raw laminated body before baking, (b) is the laminated body after baking. It is sectional drawing shown.

符号の説明Explanation of symbols

10 電子部品
11 積層体
12 コイル
12A、12B 引き出し電極部
13A、13B 外部電極
16A 第1収縮ズレ防止部
16B 第2収縮ズレ防止部
111〜114 絶縁層
121〜124 導体パターン(導電層)
DESCRIPTION OF SYMBOLS 10 Electronic component 11 Laminated body 12 Coil 12A, 12B Extraction electrode part 13A, 13B External electrode 16A 1st shrinkage | contraction deviation prevention part 16B 2nd shrinkage deviation prevention part 111-114 Insulating layer 121-124 Conductor pattern (conductive layer)

以下、図1〜図5に示す実施形態に基づいて本発明の電子部品について説明する。   Hereinafter, the electronic component of the present invention will be described based on the embodiment shown in FIGS.

本実施形態の電子部品10は、例えば図1の(a)、(b)に示すように、矩形状の積層体11と、積層体11の内部にその平面形状に即して上下方向に略螺旋状に延びるように形成されコイル12と、コイル12の上下両端部の引き出し電極部12A、12Bにそれぞれ接続され且つ積層体11の左右端面を被覆する左右一対の外部電極13A、13Bと、を備え、高周波コイル部品として構成されている。   An electronic component 10 according to the present embodiment includes, for example, a rectangular laminated body 11 and an inside of the laminated body 11 in the vertical direction according to the planar shape, as shown in FIGS. A coil 12 formed so as to extend in a spiral shape, and a pair of left and right external electrodes 13A and 13B that are connected to the extraction electrode portions 12A and 12B at both upper and lower ends of the coil 12 and cover the left and right end surfaces of the laminate 11, respectively. And is configured as a high-frequency coil component.

上記積層体11は、例えば図2に示すように、上下方向に積層された複数(図2では4層)の絶縁層111〜114と、内部のコイル12を保護する保護層115とからなっている。また、上記コイル12は、絶縁層111〜114それぞれの上面に渦巻状に形成された複数の導体パターン層121〜124と、上下の導体パターン層を接続するビア導体14(図5の(b)参照)とからなり、全体として上下方向に螺旋状に延びる矩形状のコイル12として形成されている。尚、15A、15Bはそれぞれ回路基板等の実装基板面に形成された電極に接続するための端子電極である。   For example, as shown in FIG. 2, the multilayer body 11 includes a plurality of (four layers in FIG. 2) insulating layers 111 to 114 stacked in the vertical direction and a protective layer 115 that protects the internal coil 12. Yes. The coil 12 includes a plurality of conductor pattern layers 121 to 124 formed spirally on the upper surfaces of the insulating layers 111 to 114 and via conductors 14 connecting the upper and lower conductor pattern layers (FIG. 5B). And is formed as a rectangular coil 12 that spirals in the vertical direction as a whole. Reference numerals 15A and 15B denote terminal electrodes for connection to electrodes formed on a mounting board surface such as a circuit board.

ところで、焼成して積層体11を得る時には、感光性導体ペーストの焼結に伴う収縮が感光性絶縁ペーストの焼結に伴う収縮より大きいことから、焼成時には導体パターン層121〜124のコーナー部にコーナー内側への収縮応力がかかり易い。そのため、導体パターン層121〜124は絶縁層111〜114との間の収縮挙動差によって各導体パターン層121〜124がそれぞれの絶縁層111〜114上で滑り、特にコーナー部でコーナー内側方向への位置ズレを生じ易い。   By the way, when the laminate 11 is obtained by firing, the shrinkage accompanying the sintering of the photosensitive conductor paste is larger than the shrinkage accompanying the sintering of the photosensitive insulating paste. It is easy to apply shrinkage stress to the inside of the corner. Therefore, the conductive pattern layers 121 to 124 slide on the respective insulating layers 111 to 114 due to a difference in contraction behavior between the insulating layers 111 to 114, and particularly in the corner portion toward the inside of the corner. Misalignment is likely to occur.

そこで、本実施形態では、図1の(b)、図2及び図3に示すように、矩形の渦巻状の導体パターン層121〜124の各曲折部(コーナー部)の下面に第1収縮ズレ防止部16Aがそれぞれの絶縁層111〜114内に所定の深さまで食い込むように形成され、これらの第1収縮ズレ防止部16Aはそれぞれの導体パターン層121〜124と一体化している。尚、図3では絶縁層113上に形成された導体パターン層123を例に挙げて示してある。他の導体パターン層も図3に示す導体パターン層123と同様に形成されているため、図3を参考にしながら他の導体パターン層についても説明する。   Therefore, in the present embodiment, as shown in FIGS. 1B, 2, and 3, the first contraction shift is caused on the lower surface of each bent portion (corner portion) of the rectangular spiral conductive pattern layers 121 to 124. The prevention part 16A is formed so as to bite into the respective insulating layers 111 to 114 to a predetermined depth, and these first shrinkage prevention parts 16A are integrated with the respective conductor pattern layers 121 to 124. In FIG. 3, the conductor pattern layer 123 formed on the insulating layer 113 is shown as an example. Since the other conductor pattern layers are formed in the same manner as the conductor pattern layer 123 shown in FIG. 3, the other conductor pattern layers will be described with reference to FIG.

上述のように本実施形態では、各コーナー部に第1収縮ズレ防止部16Aが設けられて、各導体パターン層121〜124がそれぞれの絶縁層111〜114に拘束されているため、焼成時に各コーナー部に収縮応力が集中的に作用しても、第1収縮ズレ防止部16Aによって各導体パターン層121〜124がそれぞれの各絶縁層111〜114に追随して収縮し、それぞれの絶縁層111〜114との間の位置ズレを防止することができる。更に、導体パターン層121〜124は、それぞれの絶縁層111〜114の上面で位置ズレすることなく、それぞれの絶縁層111〜114に追随して収縮するため、焼成前後の導体パターン層は相似形状を維持し、設計に即した形状を保持して所望の電気的特性(層間容量や電磁界分布等)を得ることができる。   As described above, in the present embodiment, the first shrinkage prevention portion 16A is provided at each corner portion, and the conductor pattern layers 121 to 124 are constrained by the respective insulating layers 111 to 114. Even if the shrinkage stress acts on the corner portion in a concentrated manner, the conductor pattern layers 121 to 124 follow the respective insulation layers 111 to 114 and shrink by the first shrinkage prevention portion 16A. Misalignment between .about.114 can be prevented. Furthermore, since the conductor pattern layers 121 to 124 are contracted following the respective insulating layers 111 to 114 without being displaced on the upper surfaces of the respective insulating layers 111 to 114, the conductor pattern layers before and after firing are similar in shape. Thus, desired electrical characteristics (interlayer capacitance, electromagnetic field distribution, etc.) can be obtained while maintaining a shape in conformity with the design.

また、各コーナー部の第1収縮ズレ防止部16Aの外径は、図3の(a)、(b)に示すように、それぞれ導体パターン層123の線幅より小径に形成されている。第1収縮ズレ防止部16Aの外径を導体パターン層123の線幅よりも小さくすることによって、後述のように絶縁層113の上面に第1収縮ズレ防止部16A用の凹陥部を設けた後、この絶縁層113の上面に導体パターン層123を位置合わせして印刷する時に、凹陥部と導体パターン層123との間に多少の位置ズレがあっても、凹陥部を導体パターン層123の領域内に収めることができる。また、第1収縮ズレ防止部16Aの絶縁層113内への食い込み深さは、導体パターン層123の絶縁層113からの位置ズレを防止することができる深さであれば良く、通常図3の(b)、(c)に示すように絶縁層113の厚さよりも浅く形成されている。但し、第1収縮ズレ防止部16Aの下方に下層の導体パターン層がなければ、第1収縮ズレ防止部16Aは、絶縁層113を貫通していても良い。   Further, the outer diameter of the first shrinkage prevention portion 16A at each corner portion is formed to be smaller than the line width of the conductor pattern layer 123, as shown in FIGS. After providing a recess for the first shrinkage prevention part 16A on the upper surface of the insulating layer 113 as described later by making the outer diameter of the first shrinkage prevention part 16A smaller than the line width of the conductor pattern layer 123. When the conductor pattern layer 123 is aligned and printed on the upper surface of the insulating layer 113, even if there is a slight misalignment between the recess and the conductor pattern layer 123, the recess is formed in the region of the conductor pattern layer 123. Can fit inside. Further, the depth of biting into the insulating layer 113 of the first shrinkage prevention part 16A may be a depth that can prevent the positional deviation of the conductor pattern layer 123 from the insulating layer 113, and is usually shown in FIG. As shown in (b) and (c), the insulating layer 113 is formed thinner than the thickness. However, if there is no lower conductive pattern layer below the first shrinkage prevention part 16A, the first shrinkage prevention part 16A may penetrate the insulating layer 113.

また、図1の(b)及び図2に示すように、コイル12の上下の引き出し電極部12A、12B両端部の下面には第1収縮ズレ防止部16Aと同種の第2収縮ズレ防止部16Bが各引き出し電極部12A、12Bと一体に形成され、それぞれの絶縁層111、114内に略同一大きさで同一の深さまで食い込むように形成されている。   Further, as shown in FIG. 1B and FIG. 2, a second shrinkage prevention part 16B of the same type as the first shrinkage prevention part 16A is formed on the lower surfaces of both ends of the upper and lower lead electrode parts 12A, 12B of the coil 12. Is formed integrally with each of the lead electrode portions 12A and 12B, and is formed so as to bite into the respective insulating layers 111 and 114 to the same depth with substantially the same size.

第2収縮ズレ防止部16Bは、引き出し電極部12Aの長手方向の両端部にそれぞれ配置され、これらの第2収縮ズレ防止部16B、16Bは、焼成時に絶縁層111に追随して長手方向(積層体11の端面に沿う方向)に収縮し、絶縁層111との間での位置ズレを防止することができる。尚、コーナー部の第2収縮ズレ防止部16Bは、第1収縮ズレ防止部16Aを兼ねる。   The second shrinkage-preventing portions 16B are respectively disposed at both ends in the longitudinal direction of the extraction electrode portion 12A. These second shrinkage-preventing portions 16B and 16B follow the insulating layer 111 during firing in the longitudinal direction (lamination). (Direction along the end surface of the body 11), and displacement between the insulating layer 111 and the insulating layer 111 can be prevented. The second shrinkage prevention unit 16B at the corner portion also serves as the first shrinkage prevention unit 16A.

また、引き出し電極部12Aと導体パターン層121との連結部となるコーナー部に配置された第2収縮ズレ防止部16B(第1収縮ズレ防止部16A)は、そのコーナー部の位置ズレを防止して引き出し電極部12Aが積層体11の内側へ引き込まれることを防止し、もって引き出し電極部12Aの長手方向の端面が積層体11の端面で確実に露出するようにしてある。   Further, the second shrinkage deviation prevention portion 16B (first shrinkage deviation prevention portion 16A) disposed at the corner portion serving as a connection portion between the lead electrode portion 12A and the conductor pattern layer 121 prevents the positional deviation of the corner portion. Thus, the lead electrode portion 12A is prevented from being drawn into the laminated body 11, so that the end face in the longitudinal direction of the lead electrode portion 12A is reliably exposed at the end face of the laminated body 11.

第1、第2収縮ズレ防止部16A、16Bの外径は、それぞれ導体パターン層の幅に収まる大きさであれば特に制限されないが、使用する露光機のアライメント(位置合わせ)精度の実力値を導体幅から差し引いた値より小さくすることが好ましく、例えば導体パターン層の幅の80〜90%の範囲が好ましい。90%を超えるとこれらを設けるための凹陥部が印刷時の導体パターン層からはみ出し、隣接するパターンとの間で電気的に短絡する虞があり、80%未満では収縮ズレ防止効果が得られない虞がある。また、第1、第2収縮ズレ防止部16A、16Bの絶縁層内への食い込み深さは、それぞれ絶縁層内に収まる深さであれば特に制限されないが、例えば絶縁層の深さの25〜50%の範囲が好ましい。50%を超えると下層の導体パターン層との間で電気的に短絡する虞があり、25%未満では収縮ズレ防止効果が得られない。   The outer diameters of the first and second shrinkage prevention parts 16A and 16B are not particularly limited as long as they are within the width of the conductor pattern layer, but the actual value of the alignment (positioning) accuracy of the exposure apparatus to be used. It is preferable to make it smaller than the value subtracted from the conductor width, for example, the range of 80 to 90% of the width of the conductor pattern layer is preferable. If it exceeds 90%, the recessed portions for providing these may protrude from the conductor pattern layer during printing, and may be electrically short-circuited between adjacent patterns. If it is less than 80%, the effect of preventing shrinkage deviation cannot be obtained. There is a fear. Further, the depth of penetration of the first and second shrinkage prevention portions 16A and 16B into the insulating layer is not particularly limited as long as it is a depth that can be accommodated in the insulating layer. A range of 50% is preferred. If it exceeds 50%, there is a risk of electrical short circuit with the lower conductor pattern layer, and if it is less than 25%, the effect of preventing shrinkage deviation cannot be obtained.

また、図3の(c)に示すように、導体パターン層123の外端部の下面には下層の導体パターン層122(図2参照)と接続するためのビア導体14が絶縁層113内に形成されている。また、導体パターン層123の内端部の上面には上層の導体パターン層124(図2参照)と接続するためのビア導体14が絶縁層114内に形成されている。そして、これらのビア導体14は、導体としての機能は勿論のこと、第1、第2収縮ズレ防止部16A、16Bと実質的に同一の機能を発揮することができる。   Further, as shown in FIG. 3C, via conductors 14 for connection to the lower conductor pattern layer 122 (see FIG. 2) are formed in the insulating layer 113 on the lower surface of the outer end portion of the conductor pattern layer 123. Is formed. A via conductor 14 is formed in the insulating layer 114 to connect to the upper conductor pattern layer 124 (see FIG. 2) on the upper surface of the inner end portion of the conductor pattern layer 123. These via conductors 14 can exhibit substantially the same function as the first and second shrinkage prevention portions 16A and 16B as well as the function as a conductor.

而して、絶縁層111〜114は、いずれもセラミック粉末を焼成することによって形成することができる。セラミック粉末は、特に制限されないが、セラミック粉末として、例えば、主成分としてKO−B−SiO系ガラス粉末を含み、副成分としてBi−B−SiO系ガラス粉末を含むものを使用することができる。副成分であるBi−B−SiO系ガラス粉末は、軟化点が450〜550℃でKO−B−SiO系ガラス粉末と比較して融点が低いため、本発明では、セラミック粉末の主成分より融点の低いガラス粉末を低融点ガラス粉末として定義する。Thus, all of the insulating layers 111 to 114 can be formed by firing ceramic powder. The ceramic powder is not particularly limited, but the ceramic powder includes, for example, K 2 O—B 2 O 3 —SiO 2 glass powder as a main component and Bi 2 O 3 —B 2 O 3 —SiO 2 as a subcomponent. What contains a system glass powder can be used. Bi 2 O 3 —B 2 O 3 —SiO 2 glass powder, which is an accessory component, has a softening point of 450 to 550 ° C. and a lower melting point than K 2 O—B 2 O 3 —SiO 2 glass powder. Therefore, in the present invention, a glass powder having a melting point lower than that of the main component of the ceramic powder is defined as a low melting point glass powder.

また、導体パターン121〜124は、いずれも金属粉末を焼成することによって形成することができる。金属粉末は、特に制限されないが、金属粉末として、例えば、銀粉末、銅粉末等を使用することができる。また、セラミック粉末としては、KO−B−SiO系ガラス粉末の他、銀粉末、銅粉末等の金属粉末と同時焼成可能なセラミックガラス粉末を二種以上適宜組み合わせて使用しても良い。The conductor patterns 121 to 124 can be formed by firing metal powder. The metal powder is not particularly limited, and for example, silver powder, copper powder, or the like can be used as the metal powder. Further, as the ceramic powder, in addition to K 2 O—B 2 O 3 —SiO 2 glass powder, two or more ceramic glass powders that can be fired simultaneously with metal powder such as silver powder and copper powder are used in appropriate combination. May be.

本実施形態の電子部品10は、リソグラフィ法を用いて製造することができる。そこで、図4を参照しながら本実施形態の電子部品10の製造方法について説明する。   The electronic component 10 of the present embodiment can be manufactured using a lithography method. Therefore, a method for manufacturing the electronic component 10 of the present embodiment will be described with reference to FIG.

本実施形態では、予め、積層体11を作製するためのベース基材としてPETフィルムを準備する。また、感光性導体ペーストとしては、例えば粒径0.5〜3.0μmの銀粉末を含むものを準備し、感光性絶縁ペーストとしては、粒径0.5〜3.0μmのセラミック粉末を含むもの準備する。このセラミック粉末は、主成分としてKO−B−SiO系ガラス粉末を含み、副成分としてBi−B−SiO系ガラス粉末を含んでいる。本実施形態では、低融点ガラス粉末がセラミック粉末中に5wt%含まれている。In this embodiment, a PET film is prepared in advance as a base substrate for producing the laminate 11. As the photosensitive conductor paste, for example, a paste containing silver powder having a particle size of 0.5 to 3.0 μm is prepared, and as the photosensitive insulating paste, ceramic powder having a particle size of 0.5 to 3.0 μm is included. Prepare things. The ceramic powder includes K 2 O-B 2 O 3 -SiO 2 based glass powder as the main component, Bi 2 O 3 -B 2 O 3 contains -SiO 2 based glass powder as a secondary component. In this embodiment, the low melting point glass powder is contained in the ceramic powder by 5 wt%.

電子部品10を製造する場合には、図4の(a)に示すようにPETフィルム100を設置し、このPETフィルム100の上面に、感光性導体ペーストを塗布した後、端子電極15A、15Bのパターンで形成された透孔を有するマスク(図示せず)を介して紫外線等の光を照射し、端子電極15A、15Bとなる部分を硬化させ、未硬化の部分を現像処理により除去して、端子電極部15A’、15B’を形成する。   When the electronic component 10 is manufactured, a PET film 100 is installed as shown in FIG. 4A, a photosensitive conductor paste is applied to the upper surface of the PET film 100, and then the terminal electrodes 15A and 15B are formed. Irradiate light such as ultraviolet rays through a mask (not shown) having a through-hole formed in a pattern, cure the portions to be the terminal electrodes 15A, 15B, remove the uncured portions by development processing, Terminal electrode portions 15A ′ and 15B ′ are formed.

その後、図4の(b)に示すようにPETフィルム100の上面に感光性絶縁ペーストを塗布した後、全面に光を照射して感光性絶縁ペーストを硬化させて絶縁層部111Aを形成した後、同図に示すように絶縁層部111Aの上面に、例えばエネルギー調整されたレーザ光Lを照射して、同図の(c)に示すように第1、第2収縮ズレ防止部16A、16Bを形成するための浅い円形状の凹陥部111B、111Cを所定のパターンで絶縁層部111Aの上面に形成する。これらの凹陥部111B、111Cを形成する方法は、凹陥部を形成する方法であればレーザ光Lを用いる方法に制限されるものではない。   Thereafter, as shown in FIG. 4B, after the photosensitive insulating paste is applied to the upper surface of the PET film 100, the entire surface is irradiated with light to cure the photosensitive insulating paste to form the insulating layer portion 111A. As shown in the figure, the upper surface of the insulating layer part 111A is irradiated with, for example, energy-adjusted laser light L, and the first and second shrinkage prevention parts 16A and 16B as shown in FIG. The shallow circular recesses 111B and 111C for forming the film are formed in a predetermined pattern on the upper surface of the insulating layer 111A. The method for forming these recessed portions 111B and 111C is not limited to the method using the laser beam L as long as it is a method for forming the recessed portions.

次いで、図4の(d)に示すように、絶縁層部111A上に感光性導体ペーストを塗布して、第1、第2収縮ズレ防止部16A、16B用の凹陥部111B、111C内に感光性導体ペーストを充填すると共に導体ペースト層121Aを同時に形成する。引き続き、同図に示すように、導体パターン層121及び引き出し電極部12Aのパターンに即した透孔を有するマスク(図示せず)を介して光UVを照射し、導体パターン層121及び引き出し電極部12Aとなる部分を硬化させ、未硬化の部分を現像処理により除去して、同図に(e)に示すように導体パターン層部121B及び引き出し電極部12A’を形成する。この時、凹陥部111Bは導体パターン層部121Bのコーナー部に位置し、凹陥部111Cは引き出し電極部12A’に配置されているため、第1、第2収縮ズレ防止部16A’、16B’が光UVの照射によって渦巻状の導体パターン層部121Aと一緒に形成され、これら以外の部分では絶縁層部111Aが露出する。   Next, as shown in FIG. 4D, a photosensitive conductive paste is applied on the insulating layer portion 111A, and the photosensitive portions are exposed in the recessed portions 111B and 111C for the first and second shrinkage prevention portions 16A and 16B. The conductive paste is filled and the conductive paste layer 121A is formed at the same time. Subsequently, as shown in the figure, the light UV is irradiated through a mask (not shown) having a through hole corresponding to the pattern of the conductor pattern layer 121 and the lead electrode portion 12A, and the conductor pattern layer 121 and the lead electrode portion. The portion to be 12A is cured, and the uncured portion is removed by development processing to form a conductor pattern layer portion 121B and a lead electrode portion 12A ′ as shown in FIG. At this time, since the recessed portion 111B is located at the corner portion of the conductor pattern layer portion 121B and the recessed portion 111C is disposed in the lead electrode portion 12A ′, the first and second contraction displacement preventing portions 16A ′ and 16B ′ are It is formed together with the spiral conductive pattern layer portion 121A by irradiation with light UV, and the insulating layer portion 111A is exposed in other portions.

次いで、絶縁層部111A及びその上面の導体パターン層部121Aと同一の要領で、絶縁層部111Aの上面に絶縁層部112A、導体パターン層部122A、絶縁層部113A、導体パターン層部123A、絶縁層部116A、導体パターン層部124A及び最上層の保護層部115Aをこの順序で順次積層して、図5の(a)に示す生の積層体11Aを得る。各導体パターン層部及び他方の引き出し電極部12B’を形成する際に、それぞれの第1、第2収縮ズレ防止部16A’、16B’及びビア導体部14Aを形成する。このようにして得られた生の積層体11Aを、所定の温度、例えば850〜900℃の温度で焼成して図5の(b)に示す積層体11を得る。   Next, in the same manner as the insulating layer portion 111A and the conductor pattern layer portion 121A on the upper surface, the insulating layer portion 112A, the conductor pattern layer portion 122A, the insulating layer portion 113A, the conductor pattern layer portion 123A, The insulating layer portion 116A, the conductor pattern layer portion 124A, and the uppermost protective layer portion 115A are sequentially laminated in this order to obtain a raw laminated body 11A shown in FIG. When forming each conductor pattern layer portion and the other lead electrode portion 12B ', the first and second shrinkage prevention portions 16A' and 16B 'and the via conductor portion 14A are formed. The raw laminate 11A thus obtained is fired at a predetermined temperature, for example, a temperature of 850 to 900 ° C. to obtain a laminate 11 shown in FIG.

本実施形態では、図5の(b)に示すように各導体パターン層121〜124それぞれのコーナー部には第1収縮ズレ防止部16Aがそれぞれ形成され、引き出し電極部12A、12Bには第2収縮ズレ防止部16Bがそれぞれ形成されているため、焼成時に、各導体パターン層121〜124はそれぞれの絶縁層111〜114に追随して収縮し、それぞれの絶縁層111〜114との間の位置ズレを防止し、もって上下の各導体パターン層121〜124を同図の(b)に一点鎖線で示すように同一位置に揃い、上下の導体パターン層の相対的な位置ズレを防止することができる。従って、コイル12は、各導体パターン層121〜124の内径にバラツキがなく同一内周面に揃い、設計に即した層間容量や電磁界分布を得ることができ、延いては所望のインダクタンス値を満足し、優れた電気的特性を得ることができる。   In the present embodiment, as shown in FIG. 5B, the first shrinkage prevention portions 16A are formed at the corner portions of the conductor pattern layers 121 to 124, respectively, and the lead electrode portions 12A and 12B have the second portions. Since the shrinkage prevention portions 16B are respectively formed, the conductive pattern layers 121 to 124 follow the respective insulating layers 111 to 114 during shrinking, and are positioned between the respective insulating layers 111 to 114. The upper and lower conductor pattern layers 121 to 124 are aligned at the same position as indicated by the alternate long and short dash line in FIG. 5B, thereby preventing the relative displacement between the upper and lower conductor pattern layers. it can. Therefore, the coil 12 has no variation in the inner diameter of each of the conductor pattern layers 121 to 124 and is aligned on the same inner peripheral surface, and can obtain an interlayer capacitance and electromagnetic field distribution in conformity with the design. Satisfactory and excellent electrical properties can be obtained.

また、引き出し電極部12A、12Bには第2収縮ズレ防止部16Bがそれぞれ形成されているため、引き出し電極部12A、12Bの端面が積層体11の端面から確実に露出し、引き出し電極12A、12Bと外部電極13A、13Bとを確実に電気的に接続することができ、不良率を低減することができる。   In addition, since the second shrinkage prevention portions 16B are formed in the extraction electrode portions 12A and 12B, the end surfaces of the extraction electrode portions 12A and 12B are surely exposed from the end surface of the multilayer body 11, and the extraction electrodes 12A and 12B. And the external electrodes 13A and 13B can be reliably electrically connected, and the defect rate can be reduced.

次に、具体的な実施例について説明する。   Next, specific examples will be described.

実施例1
本実施例では、感光性導体ペーストとして例えば粒径3μmの銀粉末を含むものを準備し、感光性絶縁ペーストとしては、粒径3μmのセラミック粉末を含むもの準備した。このセラミック粉末は、主成分としてKO−B−SiO系ガラス粉末を含み、副成分としてBi−B−SiO系ガラス粉末を含んでいる。本実施例では、低融点ガラス粉末がセラミック粉末中に5wt%含まれている。そして、本実施例では、導体パターン層121〜124のコーナー部に第1収縮ズレ防止部16Aを有し、引き出し電極部12A、12Bに第2収縮ズレ防止16Bを有しない積層体11を作製し、第1収縮ズレ防止部16Aの効果を調べた。
Example 1
In this example, a photosensitive conductor paste containing, for example, silver powder having a particle size of 3 μm was prepared, and a photosensitive insulating paste containing a ceramic powder having a particle size of 3 μm was prepared. The ceramic powder includes K 2 O-B 2 O 3 -SiO 2 based glass powder as the main component, Bi 2 O 3 -B 2 O 3 contains -SiO 2 based glass powder as a secondary component. In this example, 5 wt% of the low melting glass powder is contained in the ceramic powder. In this example, the laminate 11 having the first shrinkage prevention portion 16A at the corners of the conductor pattern layers 121 to 124 and the second electrode 12A and 12B without the second shrinkage prevention 16B is produced. The effect of the first shrinkage prevention unit 16A was examined.

本実施例では、上述の感光性導体ペースト及び感光性絶縁ペーストを用いて4層の導体パターン層からなるコイルを有する電子部品を前述した要領で作製した。各導体パターン層のコーナー部に形成された第1収縮ズレ防止部の深さは、5μmであり、その外径は導体パターン層の線幅の80%であった。この電子部品のインダクタンス値は27nHであった。   In this example, an electronic component having a coil composed of four conductive pattern layers was produced in the manner described above using the above-described photosensitive conductive paste and photosensitive insulating paste. The depth of the first shrinkage prevention portion formed at the corner portion of each conductor pattern layer was 5 μm, and the outer diameter thereof was 80% of the line width of the conductor pattern layer. The inductance value of this electronic component was 27 nH.

また、比較例として、収縮ズレ防止部を有しない従来の積層体を作製した。この積層体からなる電子部品のインダクタンス値は27nHであった。   Moreover, the conventional laminated body which does not have a shrinkage | contraction deviation prevention part was produced as a comparative example. The inductance value of the electronic component made of this laminate was 27 nH.

そして、本実施例の電子部品を切断し、その切断面における導体パターン層の位置ズレ量を測定し、その結果を表1に示した。また、本実施例の電子部品のインダクタンス値(L値)を測定した後、そのバラツキを求め、その結果を表1に示した。これらの測定は100個の電子部品について行い、その平均値を表1に示した。また、比較例の電子部品についても位置ズレ量及びバラツキを求め、その結果を表1に示した。   And the electronic component of a present Example was cut | disconnected, the positional offset amount of the conductor pattern layer in the cut surface was measured, and the result was shown in Table 1. Further, after measuring the inductance value (L value) of the electronic component of this example, the variation was obtained, and the result is shown in Table 1. These measurements were performed on 100 electronic components, and the average values are shown in Table 1. Moreover, the amount of positional deviation and variation were obtained for the electronic parts of the comparative examples, and the results are shown in Table 1.

Figure 2006123467
Figure 2006123467

表1に示す結果によれば、本実施例の電子部品は第1収縮ズレ防止部を有するため各導体パターン層の平均位置ズレ量が±10%で、インダクタンス値のバラツキが3%であった。これに対して比較例1の電子部品は平均位置ズレ量が±20%で、インダクタンス値のバラツキが5%と大きく、いずれも本実施例と比較して電気的特性に劣ることが判った。   According to the results shown in Table 1, since the electronic component of this example had the first shrinkage deviation prevention portion, the average positional deviation amount of each conductor pattern layer was ± 10%, and the variation in inductance value was 3%. . On the other hand, the electronic component of Comparative Example 1 has an average positional deviation amount of ± 20% and a large variation in inductance value of 5%, and it has been found that both have inferior electrical characteristics as compared with the present example.

実施例2
本実施例では、実施例1の電子部品の引き出し電極部に第2収縮ズレ防止部を設けた以外は、実施例1の電子部品と同一要領で電子部品を作製した。そして、この電子部品の引き出し電極部と外部電極との接続状態を調べるために、導通試験を行い、その結果を表2に示した。また、比較例1の電子部品についても同一試験を行い、その結果を表1に示した。
Example 2
In this example, an electronic component was manufactured in the same manner as the electronic component of Example 1, except that the second shrinkage prevention unit was provided in the lead electrode portion of the electronic component of Example 1. And in order to investigate the connection state of the extraction electrode part of this electronic component and an external electrode, the continuity test was done and the result was shown in Table 2. The same test was performed on the electronic component of Comparative Example 1 and the results are shown in Table 1.

Figure 2006123467
Figure 2006123467

表2に示す結果によれば、本実施例の電子部品のオープン不良率が5%であった。これに対し、比較例1の電子部品のオープン不良率は10%であり、本実施例と比較して引き出し電極部と外部電極との接触不良率が高く、歩留まりの悪いことが判った。   According to the results shown in Table 2, the open defect rate of the electronic component of this example was 5%. On the other hand, the open failure rate of the electronic component of Comparative Example 1 was 10%, and it was found that the contact failure rate between the lead electrode portion and the external electrode was higher than that of this example, and the yield was poor.

尚、上記実施形態では複数の導体パターン層からなるコイルを有する高周波コイル部品を例に挙げて本発明を説明したが、本発明の電子部品は複数個所に曲折部を有する導体パターン層を少なくとも一つ備えたものであれば良い。また、複数個所に曲折部を有する導体パターンを少なくとも一つ備えたものであれば、高周波コイル部品に何等制限されるものでもない。   In the above embodiment, the present invention has been described by taking a high-frequency coil component having a coil composed of a plurality of conductor pattern layers as an example. However, the electronic component of the present invention has at least one conductor pattern layer having bent portions at a plurality of locations. It is sufficient if it has one. Moreover, as long as at least one conductor pattern having a bent portion is provided at a plurality of locations, the high-frequency coil component is not limited.

本発明は、携帯電話等に使用される高周波コイル部品等の電子部品に好適に利用することができる。   The present invention can be suitably used for electronic components such as high-frequency coil components used in mobile phones and the like.

Claims (5)

絶縁層が複数積層された積層体と、この積層体内に形成された少なくとも一つの導体パターン層と、を備え、上記導体パターン層は、複数個所に曲折部を有する電子部品であって、上記各曲折部それぞれに上記絶縁層内に食い込む第1収縮ズレ防止部を一体的に設け、且つ、上記各第1収縮ズレ防止部は上記各曲折部の領域内にそれぞれ形成されてなることを特徴とする電子部品。   A laminate in which a plurality of insulating layers are laminated, and at least one conductor pattern layer formed in the laminate, wherein the conductor pattern layer is an electronic component having bent portions at a plurality of locations, Each of the bent portions is integrally provided with a first shrinkage deviation prevention portion that bites into the insulating layer, and each of the first shrinkage deviation prevention portions is formed in a region of each of the bent portions. Electronic parts. 上記第1収縮ズレ防止部は、絶縁層の厚さ方向の途中まで形成されてなることを特徴とする請求項1に記載の電子部品。   2. The electronic component according to claim 1, wherein the first shrinkage prevention unit is formed halfway in a thickness direction of the insulating layer. 上記導体パターン層から延設された引き出し電極部を有し、上記引き出し電極部に上記絶縁層内に食い込む第2収縮ズレ防止部を一体的に設け、且つ、上記第2収縮ズレ防止部は上記引き出し電極部の領域内に形成されてなることを特徴とする請求項1または請求項2に記載の電子部品。   A lead electrode portion extending from the conductor pattern layer, the lead electrode portion integrally provided with a second shrinkage prevention portion that bites into the insulating layer, and the second shrinkage prevention portion is The electronic component according to claim 1, wherein the electronic component is formed in a region of the extraction electrode portion. 上記第2収縮ズレ防止部は、絶縁層の厚さ方向の途中まで形成されてなることを特徴とする請求項3に記載の電子部品。   The electronic component according to claim 3, wherein the second shrinkage prevention unit is formed partway along a thickness direction of the insulating layer. 上記導体パターン層が上記絶縁層を介して上下方向に複数形成され、且つ、上下の上記導体パターン層がビア導体によって互いに電気的に接続されてなることを特徴とする請求項1〜請求項4のいずれか1項に記載の電子部品。   5. The plurality of conductor pattern layers are formed in the vertical direction through the insulating layer, and the upper and lower conductor pattern layers are electrically connected to each other by via conductors. The electronic component according to any one of the above.
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JPH1197243A (en) * 1997-09-16 1999-04-09 Tokin Corp Electronic component and its manufacture
JPH11288832A (en) * 1998-04-01 1999-10-19 Ngk Spark Plug Co Ltd Laminated inductor component and manufacture thereof
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Publication number Priority date Publication date Assignee Title
JPH1197243A (en) * 1997-09-16 1999-04-09 Tokin Corp Electronic component and its manufacture
JPH11288832A (en) * 1998-04-01 1999-10-19 Ngk Spark Plug Co Ltd Laminated inductor component and manufacture thereof
JP2004207608A (en) * 2002-12-26 2004-07-22 Tdk Corp Laminated electronic component and its manufacturing method

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