JPS6491228A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6491228A
JPS6491228A JP62247420A JP24742087A JPS6491228A JP S6491228 A JPS6491228 A JP S6491228A JP 62247420 A JP62247420 A JP 62247420A JP 24742087 A JP24742087 A JP 24742087A JP S6491228 A JPS6491228 A JP S6491228A
Authority
JP
Japan
Prior art keywords
flag
arithmetic
carry
code
integers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62247420A
Other languages
English (en)
Inventor
Takeshi Sakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62247420A priority Critical patent/JPS6491228A/ja
Priority to US07/171,581 priority patent/US5029069A/en
Publication of JPS6491228A publication Critical patent/JPS6491228A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
JP62247420A 1987-06-30 1987-09-30 Data processor Pending JPS6491228A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62247420A JPS6491228A (en) 1987-09-30 1987-09-30 Data processor
US07/171,581 US5029069A (en) 1987-06-30 1988-03-22 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62247420A JPS6491228A (en) 1987-09-30 1987-09-30 Data processor

Publications (1)

Publication Number Publication Date
JPS6491228A true JPS6491228A (en) 1989-04-10

Family

ID=17163172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62247420A Pending JPS6491228A (en) 1987-06-30 1987-09-30 Data processor

Country Status (2)

Country Link
US (1) US5029069A (ja)
JP (1) JPS6491228A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0431925A (ja) * 1990-05-29 1992-02-04 Nec Corp 演算回路
JP2013536504A (ja) * 2010-08-12 2013-09-19 アーム・リミテッド アラインメント制御
JP2014182825A (ja) * 2013-03-15 2014-09-29 Intel Corp オーバーロードチェックを実行する命令
JP2016026365A (ja) * 2009-12-22 2016-02-12 インテル・コーポレーション プロセッサ、システムオンチップ（ＳｏＣ）、ハンドヘルドデバイス、および装置

Families Citing this family (34)

* Cited by examiner, † Cited by third party
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GB2229832B (en) * 1989-03-30 1993-04-07 Intel Corp Byte swap instruction for memory format conversion within a microprocessor
JPH0474229A (ja) * 1990-07-17 1992-03-09 Toshiba Corp 情報処理装置
CA2082066C (en) * 1991-03-07 1998-04-21 James A. Wooldridge Software debugging system and method especially adapted for code debugging within a multi-architecture environment
US5680584A (en) * 1991-03-07 1997-10-21 Digital Equipment Corporation Simulator system for code execution and debugging within a multi-architecture environment
US5652869A (en) * 1991-03-07 1997-07-29 Digital Equipment Corporation System for executing and debugging multiple codes in a multi-architecture environment using jacketing means for jacketing the cross-domain calls
JP2984463B2 (ja) * 1991-06-24 1999-11-29 株式会社日立製作所 マイクロコンピュータ
US5436627A (en) * 1992-04-30 1995-07-25 Ricoh Company, Ltd. Method and system for processing mixed binary length encodings containing definite and indefinite length formats
US5717947A (en) * 1993-03-31 1998-02-10 Motorola, Inc. Data processing system and method thereof
EP1416374A3 (en) * 1993-05-27 2004-09-01 Matsushita Electric Industrial Co., Ltd. Program converting unit and processor improved in address management
JPH07114469A (ja) * 1993-10-18 1995-05-02 Mitsubishi Electric Corp データ処理装置
JP3543181B2 (ja) 1994-11-09 2004-07-14 株式会社ルネサステクノロジ データ処理装置
US5924128A (en) * 1996-06-20 1999-07-13 International Business Machines Corporation Pseudo zero cycle address generator and fast memory access
US6016395A (en) * 1996-10-18 2000-01-18 Samsung Electronics Co., Ltd. Programming a vector processor and parallel programming of an asymmetric dual multiprocessor comprised of a vector processor and a risc processor
FR2765361B1 (fr) * 1997-06-26 2001-09-21 Bull Cp8 Microprocesseur ou microcalculateur imprevisible
US6314493B1 (en) 1998-02-03 2001-11-06 International Business Machines Corporation Branch history cache
US7092869B2 (en) * 2001-11-14 2006-08-15 Ronald Hilton Memory address prediction under emulation
US7181596B2 (en) * 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7529912B2 (en) * 2002-02-12 2009-05-05 Via Technologies, Inc. Apparatus and method for instruction-level specification of floating point format
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7315921B2 (en) 2002-02-19 2008-01-01 Ip-First, Llc Apparatus and method for selective memory attribute control
US7546446B2 (en) * 2002-03-08 2009-06-09 Ip-First, Llc Selective interrupt suppression
US7395412B2 (en) * 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7380103B2 (en) * 2002-04-02 2008-05-27 Ip-First, Llc Apparatus and method for selective control of results write back
US7155598B2 (en) * 2002-04-02 2006-12-26 Ip-First, Llc Apparatus and method for conditional instruction execution
US7185180B2 (en) * 2002-04-02 2007-02-27 Ip-First, Llc Apparatus and method for selective control of condition code write back
US7373483B2 (en) * 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
US7380109B2 (en) * 2002-04-15 2008-05-27 Ip-First, Llc Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor
US8990280B2 (en) * 2005-09-30 2015-03-24 Nvidia Corporation Configurable system for performing repetitive actions
US7958181B2 (en) 2006-09-21 2011-06-07 Intel Corporation Method and apparatus for performing logical compare operations
US9747105B2 (en) 2009-12-17 2017-08-29 Intel Corporation Method and apparatus for performing a shift and exclusive or operation in a single instruction
US20140089646A1 (en) * 2012-09-27 2014-03-27 Texas Instruments Incorporated Processor with interruptable instruction execution
US10073635B2 (en) 2014-12-01 2018-09-11 Micron Technology, Inc. Multiple endianness compatibility
US10133760B2 (en) * 2015-01-12 2018-11-20 International Business Machines Corporation Hardware for a bitmap data structure for efficient storage of heterogeneous lists

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119130A (en) * 1976-03-30 1977-10-06 Ibm Oversize data detector
JPS54159831A (en) * 1978-06-07 1979-12-18 Fujitsu Ltd Adder and subtractor for numbers different in data length using counter circuit
JPS5674774A (en) * 1979-11-22 1981-06-20 Nec Corp Arithmetic circuit with overflow detector
JPS58181143A (ja) * 1982-04-15 1983-10-22 Matsushita Electric Ind Co Ltd デイジタル乗算器
JPS6243474A (ja) * 1985-08-21 1987-02-25 Sumikurosu Kogyo Kk 水不感性感圧接着剤
JPS6244833A (ja) * 1985-08-22 1987-02-26 Panafacom Ltd ｎ進数除算処理方式

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119130A (en) * 1976-03-30 1977-10-06 Ibm Oversize data detector
JPS54159831A (en) * 1978-06-07 1979-12-18 Fujitsu Ltd Adder and subtractor for numbers different in data length using counter circuit
JPS5674774A (en) * 1979-11-22 1981-06-20 Nec Corp Arithmetic circuit with overflow detector
JPS58181143A (ja) * 1982-04-15 1983-10-22 Matsushita Electric Ind Co Ltd デイジタル乗算器
JPS6243474A (ja) * 1985-08-21 1987-02-25 Sumikurosu Kogyo Kk 水不感性感圧接着剤
JPS6244833A (ja) * 1985-08-22 1987-02-26 Panafacom Ltd ｎ進数除算処理方式

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0431925A (ja) * 1990-05-29 1992-02-04 Nec Corp 演算回路
JP2016026365A (ja) * 2009-12-22 2016-02-12 インテル・コーポレーション プロセッサ、システムオンチップ（ＳｏＣ）、ハンドヘルドデバイス、および装置
JP2018160288A (ja) * 2009-12-22 2018-10-11 インテル・コーポレーション プロセッサ、方法、プログラム、および機械可読記録媒体
US10372455B2 (en) 2009-12-22 2019-08-06 Intel Corporation Hand held device to perform a bit range isolation instruction
US10579380B2 (en) 2009-12-22 2020-03-03 Intel Corporation System-on-chip (SoC) to perform a bit range isolation instruction
US10579379B2 (en) 2009-12-22 2020-03-03 Intel Corporation Processor to perform a bit range isolation instruction
US10656947B2 (en) 2009-12-22 2020-05-19 Intel Corporation Processor to perform a bit range isolation instruction
JP2013536504A (ja) * 2010-08-12 2013-09-19 アーム・リミテッド アラインメント制御
US9760374B2 (en) 2010-08-12 2017-09-12 Arm Limited Stack pointer and memory access alignment control
JP2014182825A (ja) * 2013-03-15 2014-09-29 Intel Corp オーバーロードチェックを実行する命令
US9417880B2 (en) 2013-03-15 2016-08-16 Intel Corporation Instruction for performing an overload check
US10162640B2 (en) 2013-03-15 2018-12-25 Intel Corporation Instruction for performing an overload check

Also Published As

Publication number Publication date
US5029069A (en) 1991-07-02

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