JPS6489586A - Printed board - Google Patents

Printed board

Info

Publication number
JPS6489586A
JPS6489586A JP24689287A JP24689287A JPS6489586A JP S6489586 A JPS6489586 A JP S6489586A JP 24689287 A JP24689287 A JP 24689287A JP 24689287 A JP24689287 A JP 24689287A JP S6489586 A JPS6489586 A JP S6489586A
Authority
JP
Japan
Prior art keywords
layer
hole
conductive circuit
hardened
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24689287A
Other languages
Japanese (ja)
Other versions
JPH0543311B2 (en
Inventor
Shoichi Shimizu
Koji Udagawa
Yosuke Ishiguro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP24689287A priority Critical patent/JPS6489586A/en
Publication of JPS6489586A publication Critical patent/JPS6489586A/en
Publication of JPH0543311B2 publication Critical patent/JPH0543311B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards

Abstract

PURPOSE:To facilitate manufacture and improve reliability without adhesives, by providing a sheet impregnated with a resin semi-hardened upon impregnation with a through-hole and a first conductive circuit to form the first layer, and the metal substrate with a second conductive circuit to form the second layer, and by filling the through-hole with a conductive substance under the thermocompression bonding of the first layer on the second layer. CONSTITUTION:A conductor 24 such as a copper foil is laminated on one side of an insulating sheet 23 impregnated with a resin semi-hardened upon impregna tion, and is provided with a first conductive circuit 25 and a through-hole 26 for its connection. On the other hand, a metal plate 27 such as of iron or alumin ium is clad with an insulating layer 28 of epoxy resin or the like, and a conduc tor 29 such as copper foil is laminated thereon to form a second conductive circuit 30. These are subjected to thermocompression bonding at a temperature of 140-180 deg.C pressure of 30-60kg/cm<2>, and time of 30min. Thereafter, electronic devices 32 and so forth are mounted and soldered 33. At this time, the through- hole 26 is filled with a conductor 34.
JP24689287A 1987-09-30 1987-09-30 Printed board Granted JPS6489586A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24689287A JPS6489586A (en) 1987-09-30 1987-09-30 Printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24689287A JPS6489586A (en) 1987-09-30 1987-09-30 Printed board

Publications (2)

Publication Number Publication Date
JPS6489586A true JPS6489586A (en) 1989-04-04
JPH0543311B2 JPH0543311B2 (en) 1993-07-01

Family

ID=17155293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24689287A Granted JPS6489586A (en) 1987-09-30 1987-09-30 Printed board

Country Status (1)

Country Link
JP (1) JPS6489586A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0357285U (en) * 1989-08-03 1991-05-31

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3166611B2 (en) 1996-04-19 2001-05-14 富士ゼロックス株式会社 Printed wiring board and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5593287A (en) * 1979-01-08 1980-07-15 Hitachi Ltd Method of fabricating printed circuit board
JPS59232495A (en) * 1983-06-15 1984-12-27 松下電工株式会社 Method of producing multilayer circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5593287A (en) * 1979-01-08 1980-07-15 Hitachi Ltd Method of fabricating printed circuit board
JPS59232495A (en) * 1983-06-15 1984-12-27 松下電工株式会社 Method of producing multilayer circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0357285U (en) * 1989-08-03 1991-05-31

Also Published As

Publication number Publication date
JPH0543311B2 (en) 1993-07-01

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees