JPS6488999A - Cmos shift transistor - Google Patents

Cmos shift transistor

Info

Publication number
JPS6488999A
JPS6488999A JP62245389A JP24538987A JPS6488999A JP S6488999 A JPS6488999 A JP S6488999A JP 62245389 A JP62245389 A JP 62245389A JP 24538987 A JP24538987 A JP 24538987A JP S6488999 A JPS6488999 A JP S6488999A
Authority
JP
Japan
Prior art keywords
moss
capacitor
successively
inverter
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62245389A
Other languages
Japanese (ja)
Inventor
Kazuhiko Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP62245389A priority Critical patent/JPS6488999A/en
Publication of JPS6488999A publication Critical patent/JPS6488999A/en
Pending legal-status Critical Current

Links

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  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To reduce the number of each functional element in a logic circuit constituting a register by providing a capacitor between a first and a second switching elements, accumulating an inputted signal there and successively transmitting it to a first and a second inverters. CONSTITUTION:The inputted signal VIN from a front stage shift register which is not shown by a figure is inputted to an input terminal 11. To this input terminal 11, the drain D of the N channel MOS 12 of the first switching element is connected and the drain D of the N channel MOS 13 of the second switching element is connected to a source S. Between the MOSs 12 and 13, the capacitor 14 where one end is grounded is provided and shift pulses A and B are respectively impressed on the gates of the MOSs 12 and 13. To the back stage of the MOS 13, the first inverter 15 consisting of MOSs 15-1 and 15-2 and the second inverter 16 consisting of MOSs 16-1 and 16-2 are provided in series, the MOSs 15-2 and 16-2 are successively operated by using charge accumulated in the capacitor 14 and the MOSs 15 and 16 including them are successively outputted.
JP62245389A 1987-09-29 1987-09-29 Cmos shift transistor Pending JPS6488999A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245389A JPS6488999A (en) 1987-09-29 1987-09-29 Cmos shift transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245389A JPS6488999A (en) 1987-09-29 1987-09-29 Cmos shift transistor

Publications (1)

Publication Number Publication Date
JPS6488999A true JPS6488999A (en) 1989-04-03

Family

ID=17132929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245389A Pending JPS6488999A (en) 1987-09-29 1987-09-29 Cmos shift transistor

Country Status (1)

Country Link
JP (1) JPS6488999A (en)

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