SU794668A1 - Shift register - Google Patents

Description

The invention relates to the field of microelectronics and can be applied in integrated circuits of shift registers designed for storing and processing digital and discrete analog information.

Digital and discrete-analog shift registers based on devices with charge-coupled communication (CCD) are known, for example, a shift register made on the basis of a CCD, two groups of transmitting electrodes of which are connected respectively to the first and second control buses 1J.

The disadvantage of such a shift register is the need to amplify the output signal.

Known CCD based shift registers contain output amplifiers made on the same chip.

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However, the shape of the output signals of such shift registers is strongly dependent on the parameters of the control pulse signals applied to the control rails, which makes it difficult to filter the output signal and reduces speed.

The closest to the invention to the technical essence is the shift register 4, containing a CCD, two groups of transmitting electrodes of which are connected

respectively, to the first and second control buses, a buffer stage connected to the output of the CCD, an output stage and an electronic switch connected between the buffer and output stages. The shift of information in the register occurs under the action of shifting pulses applied to one of the control buses. The output signal produced by the register in the interval between adjacent shifting pulses is amplified by the buffer cascade and fed to the input of the output cascade via an electronic key controlled by building pulses supplied to its control input. If the gating pulse declines to a level of 0.5 bf (where Uf is the amplitude of the shifting pulses) faster than the rise of the front of the shifting pulses to the same value, then between the gating pulses the voltage level at the input does not change, as memorization occurs information on the input capacitance of the output stage. Thanks to this

the dependence of the shape of the output signal on the parameters of the control pulses is reduced, filtering the output signal is facilitated. The disadvantage of such a shift register is the need to feed at least

as much as two control pulse signals, as well as the effect of the capacitance of the terminals and mounting, on the shape and interposition of the strobe and control pulses, which prevents the use of a simple generator of control pulses, reduces the range of application of the shift register and reduces its speed.

The aim of the invention is to increase the speed of the shift register and simplify it.

The goal is achieved by the fact that in the shift register containing a CCD, the first and second transmitting electrodes of which are respectively connected to the first and second control buses, the buffer stage, the input of which is connected to the output of the CCD, the output stage, which input is connected to the output of the key, the key input is connected to the output of the buffer stage, an inverter is inputted, the input of which is connected to the first control bus, the output of the inverter is connected to the second key input.

FIG. 1 is a functional diagram of the shift register; in fig. 2 is a timing diagram of the control voltages and the shape of the output signal.

The shift register contains a CCD 1, control buses 2 and 3, a buffer stage 4, an output stage 5, a switch 6, and an inverter 7.

The shift register works as follows.

The output signal produced by the CCD 1, after the end of the shift pulse, is amplified by the buffer cascade 4 and through the switch 6, for which the MOS transistor can be used, is transmitted to the input of the output stage 5. When the front of the next shift pulse rises to 0.5 f / F starts recharging the output capacitance of the CCD 1, and the voltage level at the output of the buffer stage 4 changes. However, already when the front of the shift pulse reaches a level of approximately (0.1-0.2), the UV switches to the inverter 7 and the key 6 is locked. Due to this, the information recorded on the input capacitance of the output stage 5 is maintained throughout the entire period of the shifted pulses, while the output signal has a step form, as shown in FIG. 2, for example for the case of a sinusoidal transmitted signal.

The high switching speed of the inverter 7 in the proposed shift register is easily achieved due to the small capacity of its load, which is approximately

(0.05-0.2), and the absence of the effect of mounting capacity.

The introduction of inverter 7 into the shift register reduces the number of control pulsed signals to one and increases the speed by 2-5 times, which greatly expands the scope of application of such shift registers in devices for processing digital and discrete-analog information, simplifies the design of the equipment based on them.

Claims (4)

1. The patent of France No. 2108053, cl. G PS 11/00, publ. 1972. 2. USSR author's certificate number 517085. class. H OIL 19/00, 1976. 3. USSR author's certificate number 497935, cl. H OZK 13/00, 1974. 4. Nosov, Yu. R., et al. Semiconductor devices with charge coupling. M., “Soviet Radio, 1976, p. 94, Fig. 3.8 (prototype). bj FIG / Y /  1G 1Sh1PG H. Phage: 2