KR940003248Y1 - Phase detecting circuit - Google Patents

Abstract

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Description

Phase detection circuit

1 is a conventional phase detection circuit diagram.

(A) to (i) of Figs. 2a and 2b are conventional timing diagrams.

3 is a phase detection circuit diagram of the present invention.

4a and 4b (a) to (i) is an operating timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10: first detection unit 20: second detection unit

C ₁ , C ₂ : Condenser MN ₁ ~ MN ₆ : Enmotransistor

MP ₁ to MP ₆ : PMOS transistor N ₁ , N ₂ : Inverter

NA ₁ : NANDGATE

The present invention relates to a phase detector, and more particularly, to a phase detection circuit having good economical efficiency by reducing the layout area by reducing the number of components.

In the conventional phase detection circuit, as shown in FIG. ₁ , the reset terminal R is commonly connected to two input signals U ₁ and U ₂ by NAND gates NA ₁ and NA ₂ . Input to the set terminals (S ₁ ) and (S ₂ ) of the R-S flip-flop (F / F ₁ ) and (F / F ₂ ) respectively, and to NAND gate (NA ₄ ) and (NA ₅ ) And the common input signals Q ₁ and Q _{2 of} the R-S flip-flop F / F ₁ and F / F ₂ to output the NAND gate NA ₃ accordingly. Input to the NAND gate (NA ₄ ), (NA ₅ ), respectively, and outputs the up (down) / down (down) signal from the NAND gate (NA ₄ ), (NA ₅ ) and the signal It was constructed by feeding back to NAND gates (NA ₁ ) and (NA ₂ ).

The conventional technical operation configured as described above will be described with reference to the operation timing diagrams of FIGS. 2A and 2B.

2A is an operation timing diagram when the input signal U ₁ is out of phase with other input signals U ₂ as shown in (a) and (b).

That is, as shown in (a) and (i) of FIG. 2a, first, when both the up / down signals of the output side are high level, the input signals U ₁ and U ₂ are both At low level, the NAND gates NA ₁ and NA ₂ output high levels to output nodes a and b regardless of their other inputs, as shown in (c) and (d) of FIG. The level is input to each of the input terminals of the NAND gate NA ₃ . As shown in (e) and (f) of FIG. 2, both are at a low level, and the output node e of the NAND gate NA ₃ is at a high level as in (g) of FIG. 2a. Therefore, the up / down signals finally output through the NAND gates NA ₄ and NA _{5 become} high levels.

At this time, when the input signal U ₁ becomes high level, the output node a of the NAND gate NA ₁ becomes low level, and the low-s flip-flop F / F ₁ is set by the low level. Since the output node c becomes high level, the node e and the up signal maintain high peak level.

Then, when the input signal U ₂ becomes high level, the output node b of the NAND gate NA ₂ becomes low level and its output terminal Q ₂ as the AL-S flip-flop F / F ₂ is set. The node d becomes a high level by the high signal outputted through N, and both the output node e and the down signal of the NAND gate NA _{3 become} high level.

Subsequently, when the input signal U ₁ becomes low level, the output node a of the NAND gate NA ₁ becomes my level, and the high-level flip-flop F / F ₁ is not set by this high level. The reset terminal R is also not reset by the high level output node e of the gate NA ₃ so that the R-S flip-flop F / F ₁ is in a previous state, that is, the input signal U ₁ is high. Maintain the state when it is. As a result, the output node c of the R-S flip-flop (F / F ₁ ) maintains the high level, and the output node e of the NAND gate NA ₃ also maintains the high bell, which is input to the input terminal of the NAND gate NA ₄ . As the signals are all at the high level, the NAND-combined up signal through the NAND gate NA ₄ is at the low level.

When the input signal U ₂ becomes low again, the output node b of the NAND gate NA ₂ becomes high and the high-s flip-flop F / F ₂ is not set by the high level. Since the reset terminal R of the R-S flip-flop F / F ₂ is not reset due to the high level of the NAND gate NA ₃ , the previous state is maintained, so that the R-S flip-flop F / Since the output node d of F ₂ is maintained at the high level, the node e through the NAND gate NA ₃ is at the low level.

Therefore, nodes c and d become low level soon, and up and down signals become high level.

After all, the input signal U ₁ phase is when the phase is ahead of the up signal (up) has become a low level at the falling edge of the input signal (U ₁₎ which is input a high level on the falling edge of the signal (U ₁₎ than U ₂ This comes out. At this time, the down signal keeps the high level.

On the other hand, the timing-down signal (down), like a diagram of when 2b turns the input signal U _1, this phase dwijil than U ₂ is a low level on the falling edge of the input signal (U _2), the input signal (U ₁₎ At the falling edge, a pulse that goes to the high level is output and the up signal up remains high.

However, such a conventional phase detection circuit is composed of a total of 44 MOS transistors, including 22 NMOS transistors and 22 PMOS transistors, resulting in a large layout area, which is economically unsuitable.

In order to solve this problem, the present invention provides four constituent elements that constitute eight MOS transistors for obtaining an up signal, eight MOS transistors for obtaining a down signal, and two input NAND gates for generating a discharge signal. By using the present invention, a phase detection circuit having reduced layout area during integration and improving economic efficiency was devised. Referring to the accompanying drawings, the following description is made.

3 is a phase detection circuit diagram of the present invention, as shown therein, a first detection unit 10 for detecting an up signal according to the level of an input signal U ₁ through an input terminal, and an input through an input terminal. The second and second detectors 20 and 20 detect the down signal according to the level of the signal U ₂ , and the first and second detectors are provided with the outputs of the first and second detectors 10 and 20 as inputs. And a NAND gate NA ₁ for generating a discharge signal in (10) and (20).

The first detector 10 receives the input signal U1 through the inverter N ₁ through the gate and the drain of the pimno transistor MP ₁ through the input signal U ₂ through the source is a ground capacitor. C ₁ ) is connected to the source of the PMOS transistor MP ₂ through which the input signal U ₁ is input to the gate, and the drain of the PMOS transistor MP ₂ is the NMOS transistor MN ₁ having the source grounded. ) to the gate of the NMOS transistor (MN ₂₎ coupled in series between the connection to the drain box, and as well as receiving each input an input signal (U ₂₎ to the gate PMOS and NMOS transistor (MP ₃₎ (MN ₃₎ of The gate of the NMOS transistor MN ₁ is connected to the output terminal of the NAND gate NA ₁ , and is up from the drain common connection point of the PMOS and NMOS transistor MP ₃ (MN ₂ ). Configured to detect a signal, and the second detection unit 20 redetects The configuration made of the same construction as the unit 10.

Referring to the operation and effects of the present invention configured as described above in detail.

First, a case in which the input signal U ₁ precedes U ₂ as shown in FIG. 4A will be described. As shown in (a) and (b) of FIG. 4A, the input signals U ₁ and U ₂ are all low level. when the first detecting section 10 PMOS transistor (MP ₃₎ and the second detector 20 PMOS transistor (MP ₆₎ is turned up (up, as in claim 4a-degree (g) and (h) of the ) Signal and the down signal are both at a high level.

At this time, the low level is raised by the NAND gate NA1 that receives the up signal and the down signal in the high state, and the MOS transistors MN1 and MN4 of the first and second detectors 10 and 20 are provided. As it is input to the gate, it is turned off.

In this state, when the input signal U ₁ becomes high level, the low level inverted through the inverter N ₁ is turned on as it is input to the gate of the PMOS transistor MP ₁ , and then the input signal U _2. ) Becomes a high level, the capacitor C ₁ is charged by this high level, and the node a becomes a high level as shown in Fig. 4A (c).

In addition, as the low level of the high level input signal U ₁ is inverted through the inverter N ₂ of the second detector 20 is applied to the gate of the PMOS transistor MP ₄ , the input signal U is turned on. _The capacitor C ₂ is charged by the high level of ₁ ), and the node c becomes the high level as shown in FIG. 4E (e).

Subsequently, when the input signal U ₁ is at a low level, the PMOS transistor MP ₁ is turned off and the PMOS transistor MP ₂ is turned on to charge the capacitor C ₁ signal. ₂ ), the node b is at a high level as shown in (d) of FIG. 4A, and the high level turns on the NMOS transistor MN ₂ .

At this time, since the input signal U ₂ is in the high level state, the MOS transistor MN ₃ of the first detection unit 10 is also turned on, so the up signal is applied to the MOS transistor MN ₂ (MN ₃ ). Through this, a loop is formed on the ground side to the low level.

When the up signal reaches the low level, the NAND gate NA ₁ receives the combined signal at the high level as shown in (i) of FIG. 4A and the NMOS in the first and second detection units 10 and 20. It is applied to the gate of the transistor MN ₁ (MN ₄ ) to be turned on. Accordingly, the MOS transistors MN ₁ and MN ₄ are turned on so that the potentials of the nodes b and d are discharged as shown in FIGS. 4A and 4F and the MOS transistors MN ₂ and MN ₅ are discharged. ) Is off, so the up signal (up) maintains a low level and the down signal (down) maintains a high level.

Subsequently, when the input signal U ₂ becomes low level, the PMOS transistor MP ₃ of the first detector 10 is turned on so that the up signal up becomes high level and the down signal down becomes the input signal U. _{Since 1} ) is a low level state, the PMOS transistor MP ₆ of the second detection unit 20 is turned on to maintain a high state.

On the other hand, FIG. 4B is similar to the case where the input signal U ₁ lags behind U _{2. When} the input signal U ₂ becomes low level, the down signal becomes low level and the input signal U ₁ becomes low level. Outputs to the high level, and the up signal up remains high.

As described in detail above, the present invention is composed of a total of 20 MOS transistors, including 10 MOS transistors and 10 PMOS transistors, compared to the conventional 44 MOS transistor elements, thereby reducing the layout area and thus helping to provide economic benefits. Will be.

Claims (3)

Up by the input an input signal (U ₁₎ is (up) a second detector 20 for detecting a down (down) signals by the first detection unit 10, which is input an input signal (U ₂₎ for detecting the signal And the discharge signals in the first, second detectors 10 and 20 by inputting the output up / down signals of the first and second detectors 10 and 20 as inputs. Phase detection circuit, characterized in that composed of NAND gate (NA ₁ ) to make. The PMOS transistor MP ₁ of claim 1, wherein the first detector 10 receives an input signal U ₁ as a gate through an inverter N ₁ and receives the input signal U ₂ as a source. a drain ground capacitor (C ₁₎ a via the input signal (U ₁₎ is connected to the source of the PMOS transistor (MP ₂₎ is input to the gate and drain of the PMOS transistor (MP ₂₎ is sources flowing to the ground The NMOS transistors connected in series between the PMOS and the NMOS transistors MP ₃ and MN ₃ receiving the input signal U ₂ as a gate and connected to the drains of the NMOS transistors MN _1, respectively. MN ₂ ), and the gate of the NMOS transistor MN ₁ is connected to the output terminal of the NAND gate NA ₁ , and the drain of the PMOS and NMOS transistor MP ₃ (MN ₂ ) is common. The number of elements can be reduced by configuring the detection of up signal from the connection point. The phase detection circuit, characterized in that the. 2. The phase detection circuit according to claim 1, wherein the second detector (20) has the same configuration as that of the first detector (10).