JPS6488863A - Input data control circuit - Google Patents
Input data control circuitInfo
- Publication number
- JPS6488863A JPS6488863A JP24708287A JP24708287A JPS6488863A JP S6488863 A JPS6488863 A JP S6488863A JP 24708287 A JP24708287 A JP 24708287A JP 24708287 A JP24708287 A JP 24708287A JP S6488863 A JPS6488863 A JP S6488863A
- Authority
- JP
- Japan
- Prior art keywords
- data
- rsf
- change
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To execute an optimum response to a peripheral equipment to have the various types of access styles by providing a detecting circuit to detect the change of input data and a detecting circuit to detect that the input data are not changed for a constant time, etc. CONSTITUTION:Data D from a data input terminal DIN are inputted to a delaying circuit DLY and an exclusive OR gate EOR. The gate EOR inputs the data D and the output of the circuit DLY. Then, the decidence of the data D, which are delayed only for the delaying time of the circuit DLY, and present data, namely, the change of the data D is detected and an RSF 1 (FF) is set by the output. An RSF 2 (FF) is set by the logical product signal of the output signal of the RSF 1 and the output signal of an inverter INV. Namely, the data D are not changed after one change and the data are set in case that the delaying time of the circuit DLY passes. Thus, the data are latched by a data latch DL and simultaneously, a bus cycle is ended. Then, since a CPU reads the latch data, the optimum response can be executed to the peripheral equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24708287A JPS6488863A (en) | 1987-09-30 | 1987-09-30 | Input data control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24708287A JPS6488863A (en) | 1987-09-30 | 1987-09-30 | Input data control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6488863A true JPS6488863A (en) | 1989-04-03 |
Family
ID=17158161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24708287A Pending JPS6488863A (en) | 1987-09-30 | 1987-09-30 | Input data control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6488863A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59176854A (en) * | 1983-03-28 | 1984-10-06 | Meidensha Electric Mfg Co Ltd | Memory device of computer control system |
JPS6119860B2 (en) * | 1979-09-07 | 1986-05-19 | Mitsubishi Motors Corp |
-
1987
- 1987-09-30 JP JP24708287A patent/JPS6488863A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6119860B2 (en) * | 1979-09-07 | 1986-05-19 | Mitsubishi Motors Corp | |
JPS59176854A (en) * | 1983-03-28 | 1984-10-06 | Meidensha Electric Mfg Co Ltd | Memory device of computer control system |
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