JPS55127635A - Interruption input interface - Google Patents

Interruption input interface

Info

Publication number
JPS55127635A
JPS55127635A JP3407279A JP3407279A JPS55127635A JP S55127635 A JPS55127635 A JP S55127635A JP 3407279 A JP3407279 A JP 3407279A JP 3407279 A JP3407279 A JP 3407279A JP S55127635 A JPS55127635 A JP S55127635A
Authority
JP
Japan
Prior art keywords
input
cpu
signal
interruption
rise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3407279A
Other languages
Japanese (ja)
Other versions
JPS6144355B2 (en
Inventor
Yukihiko Inagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idec Izumi Corp
Original Assignee
Idec Izumi Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Idec Izumi Corp filed Critical Idec Izumi Corp
Priority to JP3407279A priority Critical patent/JPS55127635A/en
Publication of JPS55127635A publication Critical patent/JPS55127635A/en
Publication of JPS6144355B2 publication Critical patent/JPS6144355B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To set freely the response time of an interruption input by enriching the data processing contents of CPU by sending an interruption request signal to CPU by reading information, showing the rise or fall state of an input signal, from a memory through a latch circuit.
CONSTITUTION: In an interruption input interface coupling input multiplexer 4 with the bus line of CPU, time control signal generating circuit 1 generates a time control signal repeated at fixed cycles and input multiplexer 4 selects one input signal according to this signal. Here, detection part 5 compares two states of this signal on the same input line before and after one point in time to detect whether this input line is in a rise or fall state. On the detection, latch circuit 9 reads information on the rise or fall state from memory 6 or 7 to send an interruption request signal to CPU. Consequently, the data processing contents of CPU can be enriched and the response time of an interruption input can also be set freely.
COPYRIGHT: (C)1980,JPO&Japio
JP3407279A 1979-03-22 1979-03-22 Interruption input interface Granted JPS55127635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3407279A JPS55127635A (en) 1979-03-22 1979-03-22 Interruption input interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3407279A JPS55127635A (en) 1979-03-22 1979-03-22 Interruption input interface

Publications (2)

Publication Number Publication Date
JPS55127635A true JPS55127635A (en) 1980-10-02
JPS6144355B2 JPS6144355B2 (en) 1986-10-02

Family

ID=12404052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3407279A Granted JPS55127635A (en) 1979-03-22 1979-03-22 Interruption input interface

Country Status (1)

Country Link
JP (1) JPS55127635A (en)

Also Published As

Publication number Publication date
JPS6144355B2 (en) 1986-10-02

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