JPS57160072A - Tester for entanglement of wires - Google Patents
Tester for entanglement of wiresInfo
- Publication number
- JPS57160072A JPS57160072A JP56045610A JP4561081A JPS57160072A JP S57160072 A JPS57160072 A JP S57160072A JP 56045610 A JP56045610 A JP 56045610A JP 4561081 A JP4561081 A JP 4561081A JP S57160072 A JPS57160072 A JP S57160072A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- counter
- gate
- high level
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
PURPOSE:To enable automatic detection of short-circuiting between a plurality of terminals by means of a relatively simple single logic circuit. CONSTITUTION:A counter 1 is initialized and the output of an inverter 191 is a ground potential on the output side of a decoder 9 while the outputs of all other inverters are at a high level. Therefore the output of an AND gate 231 is at a low level. A high level is applied to one input of an AND gate 232 by decoding 17 an initialized value 2 of a counter 11. Unless there is no electric short-circuiting between terminals T1 and T2, the other input of the AND gate 232 is also at a high level. A high level signal of the output is applied to an AND gate 13 and a clock signal CL2 is provided to the counter 11 giving a counted value 3. A conduction test is conducted between terminals T1 and T3... and T1 and T8 to bring the counted value up to 8. If a shortcircuit occurs between any of terminals, no clock signal comes to the counter 11, leaving the action halted thereby enables the detection of any entanglement of wires.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56045610A JPS57160072A (en) | 1981-03-30 | 1981-03-30 | Tester for entanglement of wires |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56045610A JPS57160072A (en) | 1981-03-30 | 1981-03-30 | Tester for entanglement of wires |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57160072A true JPS57160072A (en) | 1982-10-02 |
Family
ID=12724131
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56045610A Pending JPS57160072A (en) | 1981-03-30 | 1981-03-30 | Tester for entanglement of wires |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57160072A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59128666A (en) * | 1983-01-14 | 1984-07-24 | Fuji Xerox Co Ltd | Issuing device of slip, form or the like |
-
1981
- 1981-03-30 JP JP56045610A patent/JPS57160072A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59128666A (en) * | 1983-01-14 | 1984-07-24 | Fuji Xerox Co Ltd | Issuing device of slip, form or the like |
JPH0526228B2 (en) * | 1983-01-14 | 1993-04-15 | Fuji Xerox Co Ltd |
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