JPS648845B2 - - Google Patents
Info
- Publication number
- JPS648845B2 JPS648845B2 JP56017573A JP1757381A JPS648845B2 JP S648845 B2 JPS648845 B2 JP S648845B2 JP 56017573 A JP56017573 A JP 56017573A JP 1757381 A JP1757381 A JP 1757381A JP S648845 B2 JPS648845 B2 JP S648845B2
- Authority
- JP
- Japan
- Prior art keywords
- series
- control
- circuit
- control circuit
- waiting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/577—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices for plural loads
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Power Sources (AREA)
- Direct Current Feeding And Distribution (AREA)
Description
【発明の詳細な説明】
本発明は電源制御装置に関し、詳しくは情報処
理装置等の多数の機器(テープ装置、デイスク装
置、プリンタ等)に電源投入するに際し、突入電
流の重複をさけて平準化し、しかも短時間に電源
制御できるようにした制御構成に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply control device, and more specifically, when turning on power to a large number of devices such as information processing devices (tape devices, disk devices, printers, etc.), the present invention prevents duplication of inrush currents and equalizes them. , and also relates to a control configuration that enables power supply control in a short time.
従来、この種の電源制御装置は、単系列制御で
多数の機器の電源投入等を逐次行なうため、全体
の電源制御に長時間を要し、情報処理装置のシス
テム運用面からみて無駄な時間を費すという欠点
がある。これを避けるために、単系列制御で同時
に複数台の装置を扱うとシステム全体の突入電流
が重畳されるため、大容量の電源設備を用意しな
ければならなくなる。 Conventionally, this type of power supply control device sequentially turns on the power of a large number of devices using single-series control, so it takes a long time to control the entire power supply, resulting in wasted time from the perspective of system operation of the information processing device. It has the disadvantage of being expensive. In order to avoid this, if multiple devices are handled at the same time using single-series control, the inrush current of the entire system will be superimposed, so large-capacity power supply equipment must be prepared.
本発明の目的は、多系列で並行して各系列ごと
に電源制御し、しかも突入電流を重複させないよ
うにして小容量の電源設備で短時間に制御するこ
とができる電源制御装置を提供することにある。 An object of the present invention is to provide a power supply control device that can perform power control for each series in parallel in multiple series, and that can perform control in a short time using small-capacity power supply equipment without duplicating inrush currents. It is in.
本発明の制御装置は、複数の系列毎に1つの系
列制御回路と複数の装置接続回路とが接続され、
前記装置接続回路をその系統毎に系列制御回路に
よつて逐次起動制御する電源制御装置において、
異なる系列下の前記装置接続回路からの完了信号
が一定時間幅内に2つ以上入力したときは先着順
もしくはあらかじめ定めた優先順位に従つて前記
系列制御回路の順位を定める比較回路と、この比
較回路の定めた順位に従つて一定時間間隔をおい
て順次前記系列制御回路の制御を行う待合制御回
路とを備えたことを特徴とする。 In the control device of the present invention, one series control circuit and a plurality of device connection circuits are connected for each of the plurality of series,
In a power supply control device that sequentially starts and controls the device connection circuit for each system by a series control circuit,
When two or more completion signals from the device connection circuits under different series are input within a certain time width, a comparison circuit that determines the order of the series control circuits on a first-come-first-served basis or according to a predetermined priority order; The present invention is characterized by comprising a waiting control circuit that sequentially controls the series control circuits at fixed time intervals according to a predetermined order of the circuits.
次に、本発明を図面を参照して詳細に説明す
る。 Next, the present invention will be explained in detail with reference to the drawings.
図は本発明の一実施例を示すブロツク図であ
り、電源制御共通回路A、系列制御回路B1〜Bn、
装置接続回路D11〜D1m,D21〜D2m,……,Dn1
〜Dnm、待合制御回路W、比較回路C等から構
成される電源制御共通回路Aは外部から投入・切
断指示を受けると比較回路Cを起動する。比較回
路Cはあらかじめ定めた優先順位およびまたは外
部指示により起動すべき系列制御回路Bの優先順
位を決定して、待合制御回路Wに制御を渡す。例
えば、系列制御回路B1から始めて順次Bnを動作
させるものとすると、待合制御回路Wは先ず系列
制御回路B1を駆動し、その後数十ミリ秒の一定
時間間隔で順次系列制御回路B2,……,Bnを駆
動する。各系列制御回路Bi(i=1〜n)は待合制
御回路Wから駆動された後は系外下の装置接続回
路Dを順次制御して、装置接続回路Dに接続され
た図示されない装置の電源の投入・遮断等をさせ
る。例えば、系列制御回路B1は先ず装置接続回
路D11を起動し、それに接続された図示されない
装置の電源の投入・遮断等をさせる。上記装置の
電源投入等の動作はその装置の内蔵するシーケン
ス回路等の動作により複数個所の投入等がされる
場合もあり、一般に1〜2秒程度で動作が完了し
た後装置接続回路D11から完了信号が出される。
この間にも系列制御回路B2,……,Bnは数十ミ
リ秒間隔で起動されて上述と同様に系列下の各装
置接続回路Dを起動し、同様な動作を行なつてい
る。そして例えば前記装置接続回路D11から完了
信号が出されると、比較回路Cは、他の同様な完
了信号を数十ミリ秒以内に受けていないときは前
記完了信号を待合制御回路Wを介して(待合せし
ないで)前記系列制御回路B1に制御を戻す。系
列制御回路B1は、これにより装置接続回路D12を
起動し、それに接続された装置の電源投入・遮断
等をさせる。そして、前述と同様に1〜2秒後に
動作完了すると接続回路D12から完了信号が出さ
れる。若しこのとき、数十ミリ秒以内に他の同様
な完了信号が例えば接続回路D21から出されてい
たとすると、比較回路Cによつて直前(数十ミリ
秒以内)に別の完了信号があつたことを判別し、
先着の(接続回路D21からの)完了信号に対して
は前述と同様に待合制御回路Wを介して(待合せ
しないで)系列制御回路B2に制御を戻し、系列
制御回路B2は接続回路D22を起動する。一方、後
着の(接続回路D12からの)完了信号に対しては
待合制御回路Wによつて(前記系列制御回路B2
起動後)数十ミリ秒間待合せた後に系列制御回路
B1に制御を戻す。従つて、接続回路D13は接続回
路D22が起動されたのち数十ミリ秒後に起動され
ることになる。このため、電源投入時の突入電流
が重複しない。換言すれば、比較回路Cは完了信
号が数十ミリ秒以内に複数入力されたときは、先
着順に待合せ制御回路へ入力させ、待合制御回路
は先着の系列から数十ミリ秒間の時間をおいて順
次該当系列へ制御を戻すわけである。若し、複数
の完了信号が同時に比較回路Cに入力したとき
は、比較回路Cは例えばあらかじめ定めた優先順
位に従つて順位を決定して待合制御回路Wに送
る。これらの情報の授受は、例えばデジタル信号
によつて授受してもよく、または、待合制御回路
に順位づけられた待合せ端子を複数設けて、先着
順もしくは優先順位に従つて接続するようにして
もよい。要するに、先着順または所定の優先順位
に従つて順番に数十ミリ秒の突入電流期間が重畳
しないように間隔をおいて各系列に制御を戻すよ
うにすればよい。しかし、完了信号が数十ミリ秒
以内に複数発生しない場合は、完了信号後直ちに
次の装置接続回路が起動されるわけである。そし
て、完了信号が重複した場合でも数十ミリ秒後に
は次の装置接続回路が起動されるから全体の動作
時間のおくれはそれ程大きくならない。すなわ
ち、仮りに、完了信号の重複が全くない場合は、
n個の系列制御回路B1〜Bnによつて平行して各
系列下の接続回路を逐次起動するから、完了信号
間の平均時間をT秒とするとmT秒で全部の装置
の電源投入・遮断等が完了するが、もしこの間に
おいて数十回の完了信号の衝突(数十ミリ秒以内
に2以上の完了信号が発生すること)があつたと
しても、そのために延長される時間は待合せ時間
数十ミリ秒の数十倍(2〜3秒)に過ぎない。従
つて、従来の単系列によつて制御する場合に必要
とされる時間n・m・T秒のほぼ1/nの時間で
制御が完了することになり、迅速な制御がされる
という効果がある。また、完了信号が重複したと
きは数十ミリ秒の突入電流期間は次の制御を待合
せるから大きな突入電流が重複することがない。
すなわち、突入電流が平準化されるので過大な容
量の電源を必要とせず、電源設備を効率的経済的
に利用できるという効果がある。このようにn個
の系列制御回路Bが独立に平行して動作すること
によつて全体の制御時間が単系列制御に比してほ
ぼ1/nに短縮されるとともに、同時投入による
突入電流の増大が抑止できる。 The figure is a block diagram showing an embodiment of the present invention, and includes a power supply control common circuit A, series control circuits B 1 to Bn,
Device connection circuit D 11 ~ D 1 m, D 21 ~ D 2 m, ..., Dn 1
~Dnm, a waiting control circuit W, a comparison circuit C, etc. A power supply control common circuit A starts up a comparison circuit C when it receives a power-on/power-off instruction from the outside. The comparison circuit C determines the priority order of the series control circuit B to be activated based on a predetermined priority order and/or an external instruction, and passes control to the waiting control circuit W. For example, assuming that Bn is operated sequentially starting from the series control circuit B1 , the waiting control circuit W first drives the series control circuit B1 , and then sequentially drives the series control circuits B2, B2 , and Bn at fixed time intervals of several tens of milliseconds. ..., drives Bn. After each series control circuit Bi (i= 1 to n) is driven by the waiting control circuit W, it sequentially controls the device connection circuit D below the system and supplies power to the devices (not shown) connected to the device connection circuit D. Turn on/off, etc. For example, the series control circuit B 1 first activates the device connection circuit D 11 to turn on/off the power of the devices (not shown) connected thereto. The operation of turning on the power of the above device may involve turning on multiple points depending on the operation of the sequence circuit built into the device, and generally after the operation is completed in about 1 to 2 seconds, the power is turned on from the device connection circuit D 11 . A completion signal is issued.
During this time, the series control circuits B2 , . For example, when a completion signal is issued from the device connection circuit D 11 , the comparison circuit C transmits the completion signal via the waiting control circuit W if no other similar completion signal is received within several tens of milliseconds. Control is returned to the series control circuit B1 (without waiting). The series control circuit B 1 thereby activates the device connection circuit D 12 to turn on/off the power of the devices connected to it. Then, as described above, when the operation is completed after 1 to 2 seconds, a completion signal is output from the connection circuit D12 . At this time, if another similar completion signal has been output from the connection circuit D 21 within several tens of milliseconds, the comparator circuit C will detect another completion signal just before (within several tens of milliseconds). Determine whether it is hot,
For the completion signal that arrives first (from the connection circuit D 21 ), control is returned to the series control circuit B 2 via the waiting control circuit W (without waiting) as described above, and the series control circuit B 2 is sent to the connection circuit. Start D22 . On the other hand, for the later completion signal (from the connection circuit D 12 ), the waiting control circuit W sends the completion signal (from the series control circuit B 2
After startup) After waiting for several tens of milliseconds, the series control circuit
B Return control to 1 . Therefore, connection circuit D 13 will be activated several tens of milliseconds after connection circuit D 22 is activated. Therefore, inrush currents at power-on do not overlap. In other words, when multiple completion signals are input within several tens of milliseconds, the comparison circuit C inputs them to the waiting control circuit on a first-come, first-served basis, and the waiting control circuit waits several tens of milliseconds after the first-come-first-served series. Control is sequentially returned to the relevant series. If a plurality of completion signals are input to the comparison circuit C at the same time, the comparison circuit C determines the order according to, for example, a predetermined priority order and sends it to the waiting control circuit W. The information may be exchanged using, for example, digital signals, or the waiting control circuit may be provided with a plurality of ranked waiting terminals, and connections may be made on a first-come, first-served basis or according to priority. good. In short, control may be returned to each series on a first-come, first-served basis or in accordance with a predetermined priority order at intervals so that inrush current periods of several tens of milliseconds do not overlap. However, if multiple completion signals are not generated within several tens of milliseconds, the next device connection circuit is activated immediately after the completion signal. Even if the completion signals overlap, the next device connection circuit will be activated after several tens of milliseconds, so the delay in the overall operation time will not be that large. In other words, if there is no duplication of completion signals,
Since the connection circuits under each series are sequentially activated in parallel by n series control circuits B1 to Bn, if the average time between completion signals is T seconds, all devices can be powered on and off in mT seconds. etc. are completed, but even if there are dozens of completion signal collisions (two or more completion signals are generated within several tens of milliseconds) during this period, the time extended due to this is the waiting time. It is only several dozen times ten milliseconds (2 to 3 seconds). Therefore, the control can be completed in approximately 1/n of the time required for conventional single-sequence control, which is approximately 1/n of the time required for conventional single-sequence control, resulting in the effect of rapid control. be. Furthermore, when completion signals overlap, the next control is waited for during the inrush current period of several tens of milliseconds, so large inrush currents do not overlap.
That is, since the inrush current is leveled, there is no need for a power supply with an excessive capacity, and the power supply equipment can be used efficiently and economically. By operating n series control circuits B independently and in parallel in this way, the overall control time is shortened to approximately 1/n compared to single series control, and the inrush current due to simultaneous input is reduced. Growth can be suppressed.
上述は、切断動作も投入動作に含めて述べてい
るが、切断動作では待合せの必要がないから、比
較回路Cから待合制御回路Wを経由し、時間差を
設けないで系列制御回路Bに制御を戻すようにす
ることもできる。例えば待合制御回路Wから投入
制御のみを禁止する信号を一定期間出すようにす
れば、遮断制御は直ちに行うことができる。 The above description includes the cutting operation in the closing operation, but since there is no need for waiting in the cutting operation, control is sent from the comparison circuit C to the series control circuit B via the waiting control circuit W without providing a time difference. You can also set it back. For example, if the waiting control circuit W issues a signal for a certain period of time to prohibit only the input control, the disconnection control can be performed immediately.
以上のように、本願発明においては複数の系列
が並行して非同期に電源起動の制御ができ、系列
間における突入電流期間重複を避けることができ
るように構成されているので、制御時間を大幅に
短縮し、しかも電源容量を効率的に使用できる優
れた効果が得られる。 As described above, in the present invention, the power supply start-up can be controlled asynchronously for multiple series in parallel, and the inrush current period overlap between the series can be avoided, so the control time can be significantly reduced. This provides an excellent effect of shortening the time and efficiently using the power supply capacity.
図は本発明の一実施例を示すブロツク図であ
る。
図において、Aは電源制御共通回路、B1〜Bn
は系列制御回路、D11〜D1m,D21〜D2m,……,
Dn1〜Dnmは装置接続回路、W……待合制御回
路、C……比較回路。
The figure is a block diagram showing one embodiment of the present invention. In the figure, A is a power supply control common circuit, B 1 to Bn
is a series control circuit, D 11 ~ D 1 m, D 21 ~ D 2 m, ...,
Dn 1 to Dnm are device connection circuits, W...waiting control circuit, C...comparison circuit.
Claims (1)
装置接続回路とが接続され、前記装置接続回路を
その系統毎に系列制御回路によつて逐次起動制御
する電源制御装置において、 異なる系列下の前記装置接続回路からの完了信
号が一定時間幅内に2つ以上入力したときは先着
順もしくはあらかじめ定めた優先順位に従つて前
記系列制御回路の順位を定める比較回路と、 この比較回路の定めた順位に従つて一定時間間
隔をおいて順次前記系列制御回路の制御を行う待
合制御回路と を備えたことを特徴とする電源制御装置。[Scope of Claims] 1. A power supply control device in which one series control circuit and a plurality of device connection circuits are connected to each of a plurality of series, and the device connection circuits are sequentially activated and controlled by the series control circuit for each of the series. a comparison circuit that determines the order of the series control circuits on a first-come-first-served basis or according to a predetermined priority order when two or more completion signals from the device connection circuits under different series are input within a certain time width; A power supply control device comprising: a waiting control circuit that sequentially controls the series control circuits at predetermined time intervals according to the order determined by the comparison circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56017573A JPS57132224A (en) | 1981-02-10 | 1981-02-10 | Power source controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56017573A JPS57132224A (en) | 1981-02-10 | 1981-02-10 | Power source controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57132224A JPS57132224A (en) | 1982-08-16 |
JPS648845B2 true JPS648845B2 (en) | 1989-02-15 |
Family
ID=11947647
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56017573A Granted JPS57132224A (en) | 1981-02-10 | 1981-02-10 | Power source controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57132224A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6091822A (en) * | 1983-10-24 | 1985-05-23 | 富士通株式会社 | Power source control circuit |
JPH06230862A (en) * | 1993-02-03 | 1994-08-19 | Shinko Seisakusho Co Ltd | Terminal equipment on/off time reserving system device and automatic power supply control device |
JPH08202468A (en) * | 1995-01-27 | 1996-08-09 | Hitachi Ltd | Multiprocessor system |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5230338B2 (en) * | 1974-02-21 | 1977-08-08 | ||
JPS53138640A (en) * | 1977-05-10 | 1978-12-04 | Fujitsu Ltd | Power source throw-in system |
-
1981
- 1981-02-10 JP JP56017573A patent/JPS57132224A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS57132224A (en) | 1982-08-16 |
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