JPS59142655A - Memory control system capable of simultaneous access - Google Patents

Memory control system capable of simultaneous access

Info

Publication number
JPS59142655A
JPS59142655A JP1552883A JP1552883A JPS59142655A JP S59142655 A JPS59142655 A JP S59142655A JP 1552883 A JP1552883 A JP 1552883A JP 1552883 A JP1552883 A JP 1552883A JP S59142655 A JPS59142655 A JP S59142655A
Authority
JP
Japan
Prior art keywords
memory
memory area
control part
area
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1552883A
Inventor
Yoshihisa Shiomi
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP1552883A priority Critical patent/JPS59142655A/en
Publication of JPS59142655A publication Critical patent/JPS59142655A/en
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To enhance the use efficiency of a memory and make high-speed transfer of data possible, by dividing a memory area of a main storage device to plural areas and providing a memory control part for each divided area to make the simultaneous access to different memories possible. CONSTITUTION:The memory of a main storage device MM is divided to memory areas A and B. A channel control part CHC of a channel device (DCH) identifies whether the data area designated by a channel word CHW is the memory area A or the memory area B. By this identification, data transfer to the memory area B is performed when data transfer to the memory area B is not performed even if data transfer to the memory area A is executed. The competition for the memory access to the memory area A to a central control part CC and a data transfer control part DTC.A of the device DCH is monitored and controlled by a memory control part MMC.A, and that to the memory area B is controlled by a control part MMC.B. Thus, the memory area is divided to improve the use efficiency.
JP1552883A 1983-02-03 1983-02-03 Memory control system capable of simultaneous access Pending JPS59142655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1552883A JPS59142655A (en) 1983-02-03 1983-02-03 Memory control system capable of simultaneous access

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1552883A JPS59142655A (en) 1983-02-03 1983-02-03 Memory control system capable of simultaneous access

Publications (1)

Publication Number Publication Date
JPS59142655A true JPS59142655A (en) 1984-08-15

Family

ID=11891305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1552883A Pending JPS59142655A (en) 1983-02-03 1983-02-03 Memory control system capable of simultaneous access

Country Status (1)

Country Link
JP (1) JPS59142655A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1403772A1 (en) * 2002-09-30 2004-03-31 Telefonaktiebolaget Lm Ericsson Method and memory controller for scalable multi-channel memory access
WO2004029816A3 (en) * 2002-09-30 2004-08-12 Attila Berenyi Method and memory controller for scalable multi-channel memory access
US20090132847A1 (en) * 2007-11-21 2009-05-21 Fujitsu Limited Information processing apparatus having memory clock setting function and memory clock setting method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1403772A1 (en) * 2002-09-30 2004-03-31 Telefonaktiebolaget Lm Ericsson Method and memory controller for scalable multi-channel memory access
WO2004029816A3 (en) * 2002-09-30 2004-08-12 Attila Berenyi Method and memory controller for scalable multi-channel memory access
US7231484B2 (en) 2002-09-30 2007-06-12 Telefonaktiebolaget Lm Ericsson (Publ) Method and memory controller for scalable multi-channel memory access
US20090132847A1 (en) * 2007-11-21 2009-05-21 Fujitsu Limited Information processing apparatus having memory clock setting function and memory clock setting method

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