JPS6486794A - Image memory controller - Google Patents

Image memory controller

Info

Publication number
JPS6486794A
JPS6486794A JP62245480A JP24548087A JPS6486794A JP S6486794 A JPS6486794 A JP S6486794A JP 62245480 A JP62245480 A JP 62245480A JP 24548087 A JP24548087 A JP 24548087A JP S6486794 A JPS6486794 A JP S6486794A
Authority
JP
Japan
Prior art keywords
frame
read out
image memory
phase
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62245480A
Other languages
Japanese (ja)
Inventor
Kenji Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62245480A priority Critical patent/JPS6486794A/en
Publication of JPS6486794A publication Critical patent/JPS6486794A/en
Pending legal-status Critical Current

Links

Landscapes

  • Color Television Systems (AREA)

Abstract

PURPOSE:To shift the phase of a burst signal by 180 deg. between fields at the time of reproducing a still picture with a simple constitution by switching the initial value of a horizontal counting means so as to shift the phase of a chrominance subcarrier read out from an image memory at every frame. CONSTITUTION:In case of reproducing the still picture, a readout pulse RE is generated after writing data of one field on the image memory 24, and the data of one field is read out repeatedly. In such a case, a frame discrimination circuit 30 to keep the continuity of the burst signal is provided, and a frame discrimination pulse LD which repeats an 'H' level and an 'L' level at a frame cycle is inputted to a horizontal counter 25. Since the output data HADRS of the horizontal counter 25 designates a readout address in a horizontal direction, the data can be read out by a clock CK from a timing signal generation circuit 23 earlier by two clocks in an odd frame compared with an even frame. Here, since the frequency of the CK is provided with the frequency of four times that of the chrominance subcarrier, the phase of the burst signal read out at the odd frame is inverted by 180 deg..
JP62245480A 1987-09-29 1987-09-29 Image memory controller Pending JPS6486794A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245480A JPS6486794A (en) 1987-09-29 1987-09-29 Image memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245480A JPS6486794A (en) 1987-09-29 1987-09-29 Image memory controller

Publications (1)

Publication Number Publication Date
JPS6486794A true JPS6486794A (en) 1989-03-31

Family

ID=17134288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245480A Pending JPS6486794A (en) 1987-09-29 1987-09-29 Image memory controller

Country Status (1)

Country Link
JP (1) JPS6486794A (en)

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