JPS6468092A - Digital video signal processing circuit - Google Patents

Digital video signal processing circuit

Info

Publication number
JPS6468092A
JPS6468092A JP62224519A JP22451987A JPS6468092A JP S6468092 A JPS6468092 A JP S6468092A JP 62224519 A JP62224519 A JP 62224519A JP 22451987 A JP22451987 A JP 22451987A JP S6468092 A JPS6468092 A JP S6468092A
Authority
JP
Japan
Prior art keywords
reading
memories
writing
signal processing
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62224519A
Other languages
Japanese (ja)
Inventor
Masahiko Motai
Seiichi Tanaka
Koichi Kurihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba Audio Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Audio Video Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP62224519A priority Critical patent/JPS6468092A/en
Publication of JPS6468092A publication Critical patent/JPS6468092A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a data omission and to obtain a stable time axis fluctuation correction by giving a time difference between the reading reset pulse of a chrominance signal and the reading reset pulse of a luminance signal. CONSTITUTION:In a recording mode, an output obtained from a crystal voltage control oscillator 77 is made into a clock, it is used for the writing and reading of a first and a second memories 71 and 72 and the time difference is given to the pulses for the writing reset and for the reading reset to the first memory 71. On the other hand, in a reproducing mode, the output of the crystal voltage controller oscillator 77 is used as a reading dedicated clock to the first and the second memories 71 and 72 and the output of a voltage control oscillator 75 is used as a writing dedicated clock to the first and the second memories 71 and 72. Thus, an exact and stable signal processing can be executed.
JP62224519A 1987-09-08 1987-09-08 Digital video signal processing circuit Pending JPS6468092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62224519A JPS6468092A (en) 1987-09-08 1987-09-08 Digital video signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62224519A JPS6468092A (en) 1987-09-08 1987-09-08 Digital video signal processing circuit

Publications (1)

Publication Number Publication Date
JPS6468092A true JPS6468092A (en) 1989-03-14

Family

ID=16815068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62224519A Pending JPS6468092A (en) 1987-09-08 1987-09-08 Digital video signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6468092A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03186090A (en) * 1989-12-15 1991-08-14 Sony Corp Video signal reproducing device
KR100791614B1 (en) * 2006-04-24 2008-01-03 채귀남 Running circuit of a grinder for a brake-disk

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03186090A (en) * 1989-12-15 1991-08-14 Sony Corp Video signal reproducing device
KR100791614B1 (en) * 2006-04-24 2008-01-03 채귀남 Running circuit of a grinder for a brake-disk

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