JPS6486787A - Automatic chrominance signal control circuit - Google Patents

Automatic chrominance signal control circuit

Info

Publication number
JPS6486787A
JPS6486787A JP24546887A JP24546887A JPS6486787A JP S6486787 A JPS6486787 A JP S6486787A JP 24546887 A JP24546887 A JP 24546887A JP 24546887 A JP24546887 A JP 24546887A JP S6486787 A JPS6486787 A JP S6486787A
Authority
JP
Japan
Prior art keywords
signal
adder
xcb
xcf
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24546887A
Other languages
Japanese (ja)
Inventor
Toru Miyazaki
Seijirou Yasuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24546887A priority Critical patent/JPS6486787A/en
Publication of JPS6486787A publication Critical patent/JPS6486787A/en
Pending legal-status Critical Current

Links

Landscapes

  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To improve fast responsiveness for change in an input burst signal level and stability for a noise by utilizing the fast responsiveness of a feedback type automatic color control circuit and the stability for the noise of a feed forward type automatic color control circuit. CONSTITUTION:A burst sampling circuit 12 samples a burst signal Ub(n). The Ub(n) is multiplied by a control signal Xc(n) by a multiplier 14, and is derived as an output signal Y(n). The subtraction processing of a reference signal r(n) and the signal Y(n) is performed at an adder 16, and a differential signal becomes a signal Xcb(n) via a non-linear circuit 18, an integrator 19, and a coefficient multiplier 20, and is supplied to the input terminal on one side of an adder 21. Meanwhile, an arithmetic operation of r(n)/Ub(n) is performed at a signal conversion circuit 31, and its output becomes a signal Xcf(n) via a coefficient multiplier 32 and an integrator 33, and is supplied to the adder 21. The adder 21 adds the Xcb(n) and the Xcf(n), and outputs the Xc(n). Control is performed by the Xcb(n) while a difference between the Ub(n) and the Y(n) is large, and by the Xcf(n) after a control state is stabilized.
JP24546887A 1987-09-29 1987-09-29 Automatic chrominance signal control circuit Pending JPS6486787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24546887A JPS6486787A (en) 1987-09-29 1987-09-29 Automatic chrominance signal control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24546887A JPS6486787A (en) 1987-09-29 1987-09-29 Automatic chrominance signal control circuit

Publications (1)

Publication Number Publication Date
JPS6486787A true JPS6486787A (en) 1989-03-31

Family

ID=17134109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24546887A Pending JPS6486787A (en) 1987-09-29 1987-09-29 Automatic chrominance signal control circuit

Country Status (1)

Country Link
JP (1) JPS6486787A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03145380A (en) * 1989-10-31 1991-06-20 Sony Corp Automatic picture quality adjustor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03145380A (en) * 1989-10-31 1991-06-20 Sony Corp Automatic picture quality adjustor

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