JPS648649A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS648649A
JPS648649A JP16489787A JP16489787A JPS648649A JP S648649 A JPS648649 A JP S648649A JP 16489787 A JP16489787 A JP 16489787A JP 16489787 A JP16489787 A JP 16489787A JP S648649 A JPS648649 A JP S648649A
Authority
JP
Japan
Prior art keywords
pin
plating
lead
layer
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16489787A
Other languages
Japanese (ja)
Inventor
Satoshi Yoshimura
Yoshinori Takasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP16489787A priority Critical patent/JPS648649A/en
Publication of JPS648649A publication Critical patent/JPS648649A/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve solderability through a simple plating structure and to provide excellent electrical and mechanical reliability at the time of mounting on a mother board by solder plating a metallic lead pin front layer, and forming a lead plating as its base plating. CONSTITUTION:After a plating layer 3 is formed of copper, nickel on a front layer of a lead pin 1 with kovar-42 alloy-phosphorus bronze as a material, sole lead is plated, and a solder plating layer 5 having 53:37 or 90:10 of composition ratio of tin:lead is further formed. A plating layer 3 of copper, nickel and a plating layer 4 of sole lead, and further a solder plating layer 5 are formed in advance on the front layer of the pin 1, and the pin 1 is engaged to be temporarily clamped within the through-hole 10 of a substrate 6 for placing a semiconductor in this state. Thereafter, the pin 1 is dipped in melted solder path to bond the pin 1 to the through-hole 10 with the solder, and the layer 6 is further formed on the pin 1.
JP16489787A 1987-06-30 1987-06-30 Semiconductor device Pending JPS648649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16489787A JPS648649A (en) 1987-06-30 1987-06-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16489787A JPS648649A (en) 1987-06-30 1987-06-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS648649A true JPS648649A (en) 1989-01-12

Family

ID=15801944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16489787A Pending JPS648649A (en) 1987-06-30 1987-06-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS648649A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528873B1 (en) * 1996-01-16 2003-03-04 Texas Instruments Incorporated Ball grid assembly with solder columns

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730353A (en) * 1980-07-30 1982-02-18 Nec Corp Semiconductor device
JPS63187656A (en) * 1987-01-30 1988-08-03 Furukawa Electric Co Ltd:The Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730353A (en) * 1980-07-30 1982-02-18 Nec Corp Semiconductor device
JPS63187656A (en) * 1987-01-30 1988-08-03 Furukawa Electric Co Ltd:The Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528873B1 (en) * 1996-01-16 2003-03-04 Texas Instruments Incorporated Ball grid assembly with solder columns

Similar Documents

Publication Publication Date Title
KR970073262A (en) Solder Method
HK105192A (en) Method of mounting refined contact surfaces on a substrate and substrate provided with such contact surfaces
CA2214130A1 (en) Assemblies of substrates and electronic components
EP0126164A4 (en) Method of connecting double-sided circuits.
JPS648649A (en) Semiconductor device
JPS5618448A (en) Composite electronic part
JPS6130439B2 (en)
JPS647542A (en) Formation of bump
JPS6489350A (en) Package for containing semiconductor element
JPS6486527A (en) Ccb tape carrier
JPS55108757A (en) Semiconductor device
MY128103A (en) Electrodeposition of low temperature, high conductivity, powder materials for electrically conductive paste formulations
JPS5718347A (en) Mounting structure of ic
JPS57130443A (en) Substrate for hybrid integrated circuit
JPS6417449A (en) Formation of bump electrode of semiconductor device
JPS6489547A (en) Board for mounting semiconductor element
JPS6481344A (en) Bump and formation thereof
JPS6472590A (en) Method of mounting component of aluminum conductor circuit substrate
JPS6417450A (en) Formation of bump
JPS56100430A (en) Fixing method for power transistor to substrate
JPS6424494A (en) Formation of solder layer on printed wiring board
JPS57143835A (en) Mounting method of ic
JPS58221667A (en) Soldering method of chip parts
JPS56120147A (en) Integrated circuit package
JPS5759343A (en) Surface treating method for circuit substrate