JPS6486243A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6486243A
JPS6486243A JP24506287A JP24506287A JPS6486243A JP S6486243 A JPS6486243 A JP S6486243A JP 24506287 A JP24506287 A JP 24506287A JP 24506287 A JP24506287 A JP 24506287A JP S6486243 A JPS6486243 A JP S6486243A
Authority
JP
Japan
Prior art keywords
registered
instruction
data
address
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24506287A
Other languages
Japanese (ja)
Other versions
JPH0769819B2 (en
Inventor
Takeshi Nishikawa
Norio Hiuga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Computertechno Ltd
Original Assignee
NEC Corp
NEC Computertechno Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Computertechno Ltd filed Critical NEC Corp
Priority to JP62245062A priority Critical patent/JPH0769819B2/en
Publication of JPS6486243A publication Critical patent/JPS6486243A/en
Publication of JPH0769819B2 publication Critical patent/JPH0769819B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the delay of the starting of a load instruction by executing the non-processed storing instruction passing propriety decision in parallel to an address directory index action. CONSTITUTION:When a load instruction is executed, a buffer part 2 checks whether or not the data to be loaded are registered into a data entry 5 in the buffer part 2, by indexing an address directory 6. Further, the buffer part 2 checks whether or not the same address as the load instruction is registered to stacks 10 and 11 for storing control information in parallel. The aimed data are registered into the data entry 5, the storing instruction of the same address as the load address is not registered in control information stacks 10 and 11, and only then, the load instruction is executed and the data registered in the data entry 5 are sent to an instruction executing part 3.
JP62245062A 1987-09-28 1987-09-28 Information processing equipment Expired - Fee Related JPH0769819B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245062A JPH0769819B2 (en) 1987-09-28 1987-09-28 Information processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245062A JPH0769819B2 (en) 1987-09-28 1987-09-28 Information processing equipment

Publications (2)

Publication Number Publication Date
JPS6486243A true JPS6486243A (en) 1989-03-30
JPH0769819B2 JPH0769819B2 (en) 1995-07-31

Family

ID=17128020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245062A Expired - Fee Related JPH0769819B2 (en) 1987-09-28 1987-09-28 Information processing equipment

Country Status (1)

Country Link
JP (1) JPH0769819B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741742A (en) * 1980-08-22 1982-03-09 Nec Corp Information processor
JPS5948879A (en) * 1982-09-10 1984-03-21 Hitachi Ltd Storage control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741742A (en) * 1980-08-22 1982-03-09 Nec Corp Information processor
JPS5948879A (en) * 1982-09-10 1984-03-21 Hitachi Ltd Storage control system

Also Published As

Publication number Publication date
JPH0769819B2 (en) 1995-07-31

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees