JPS6485740A - Manufacture of multi-layer laminate - Google Patents

Manufacture of multi-layer laminate

Info

Publication number
JPS6485740A
JPS6485740A JP62242046A JP24204687A JPS6485740A JP S6485740 A JPS6485740 A JP S6485740A JP 62242046 A JP62242046 A JP 62242046A JP 24204687 A JP24204687 A JP 24204687A JP S6485740 A JPS6485740 A JP S6485740A
Authority
JP
Japan
Prior art keywords
wiring board
adhesive material
bonding
circuits
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62242046A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0427021B2 (enrdf_load_stackoverflow
Inventor
Takeshi Kano
Toru Higuchi
Muneisa Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62242046A priority Critical patent/JPS6485740A/ja
Publication of JPS6485740A publication Critical patent/JPS6485740A/ja
Publication of JPH0427021B2 publication Critical patent/JPH0427021B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Landscapes

  • Laminated Bodies (AREA)
  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP62242046A 1987-09-26 1987-09-26 Manufacture of multi-layer laminate Granted JPS6485740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242046A JPS6485740A (en) 1987-09-26 1987-09-26 Manufacture of multi-layer laminate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242046A JPS6485740A (en) 1987-09-26 1987-09-26 Manufacture of multi-layer laminate

Publications (2)

Publication Number Publication Date
JPS6485740A true JPS6485740A (en) 1989-03-30
JPH0427021B2 JPH0427021B2 (enrdf_load_stackoverflow) 1992-05-08

Family

ID=17083463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242046A Granted JPS6485740A (en) 1987-09-26 1987-09-26 Manufacture of multi-layer laminate

Country Status (1)

Country Link
JP (1) JPS6485740A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106714476A (zh) * 2017-02-15 2017-05-24 昆山大洋电路板有限公司 一种新型四层板盲台阶加工工艺
CN107379557A (zh) * 2016-05-03 2017-11-24 利萨·德雷克塞迈尔有限责任公司 焊接构件的方法和装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107379557A (zh) * 2016-05-03 2017-11-24 利萨·德雷克塞迈尔有限责任公司 焊接构件的方法和装置
CN107379557B (zh) * 2016-05-03 2021-02-12 利萨·德雷克塞迈尔有限责任公司 焊接构件的方法和装置
CN106714476A (zh) * 2017-02-15 2017-05-24 昆山大洋电路板有限公司 一种新型四层板盲台阶加工工艺

Also Published As

Publication number Publication date
JPH0427021B2 (enrdf_load_stackoverflow) 1992-05-08

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