JPS6485408A - Automatic zero circuit - Google Patents
Automatic zero circuitInfo
- Publication number
- JPS6485408A JPS6485408A JP62242929A JP24292987A JPS6485408A JP S6485408 A JPS6485408 A JP S6485408A JP 62242929 A JP62242929 A JP 62242929A JP 24292987 A JP24292987 A JP 24292987A JP S6485408 A JPS6485408 A JP S6485408A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- gate
- fet switch
- offset
- fets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To reduce both offset and offset drift by canceling the electric charge injected from a gate terminal of an FET switch to an RC filter by an electric charge injected from the other terminal of the FET circuit. CONSTITUTION:The capacitance between both gates of two FETs Q3, Q4 in an FET circuit 4 is the combination of parallel connection between the series connection of two gate-source capacitors and the series connection of two gate- rain capacitors. Since the same characteristic of FETs Q3, Q4 is adopted for the FET switch Q1, the FETs are of nearly the same capacitor characteristic as that of the FET switch Q1 including the temperature characteristic. Since the gate terminal of the FET Q4 is driven by a signal in opposite phase to the gate input of the FET switch Q1, that is, in phase with the gate input of the FET switch Q2, a spike current in opposite polarity with the spike current from the gate terminal of the FET switch Q1 is injected to a capacitor C2. Thus, both the offset and offset drift are reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62242929A JPH0732331B2 (en) | 1987-09-28 | 1987-09-28 | Auto zero circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62242929A JPH0732331B2 (en) | 1987-09-28 | 1987-09-28 | Auto zero circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6485408A true JPS6485408A (en) | 1989-03-30 |
JPH0732331B2 JPH0732331B2 (en) | 1995-04-10 |
Family
ID=17096315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62242929A Expired - Lifetime JPH0732331B2 (en) | 1987-09-28 | 1987-09-28 | Auto zero circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0732331B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002237744A (en) * | 2001-02-08 | 2002-08-23 | Hioki Ee Corp | Fet switch and automatic zero correction circuit |
JP2011242370A (en) * | 2010-05-21 | 2011-12-01 | Renesas Electronics Corp | Impedance detection circuit and adjustment method of impedance detection circuit |
-
1987
- 1987-09-28 JP JP62242929A patent/JPH0732331B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002237744A (en) * | 2001-02-08 | 2002-08-23 | Hioki Ee Corp | Fet switch and automatic zero correction circuit |
JP2011242370A (en) * | 2010-05-21 | 2011-12-01 | Renesas Electronics Corp | Impedance detection circuit and adjustment method of impedance detection circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0732331B2 (en) | 1995-04-10 |
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