SU1126943A1 - Comparator based on insulated-gate field-effect transistors - Google Patents

Abstract

A MOSFET TRANSFER COMPARATOR containing a differential stage, two capacitors, two transistors, each of which is connected to a direct input and an inverse output, respectively, and between the inverse input and the forward output of the differential stage, the direct and inverse inputs of which are connected respectively, to the first terminals of the first and second capacitors, and the gates of the transistors are connected to the control signal bus, which also, in order to improve accuracy by increasing the gain, does not The third, fourth, fifth, sixth transistors and two additional capacitors are introduced, with each additional capacitor being connected respectively between the direct input and. the output and inverse input and output of the differential stage, the third and fourth, fifth and sixth transistors are connected in series and connected to the input signal buses, and the gates of the third and sixth, fourth and fifth transistors are connected respectively to the paraphase control signal buses and the connection points .the third and fourth, fifth and sixth transistors are connected respectively to the second terminals of the second and -first capacitors.

Description

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The invention relates to the field of pulsed technology and can be used in information transformers as well as monitoring devices.

Comparators are known that contain a cascade with direct and inverse inputs and outputs 8 and two switching transistors in the feedback circuit in each shoulder of the differential cascade.

A disadvantage of the known circuits is low accuracy due to the low gain of the differential stage.

The closest in technical essence to this is a comparator on MDP transistors containing a differential stage, two capacitors, two transistors, each of which is connected respectively between a forward input and an inverse output and between an inverse input and a forward output of a differential cascade, direct and inverse outputs of which are connected respectively to the first terminals of the first and second capacitors, and the transistor gates are connected to the control panel D1-: x signals 2),

The disadvantage of such a device is: low accuracy due to low gain.

The purpose of the invention is to increase the accuracy by increasing the gain,

R/,; Achieving the goal of setting 3 a comparator on MOS transistors has two different differential stages: govdangator, two transistors each, each of which is connected between the input and the inverted output and the Meladu 7dnvny1 input and the direct output of the differential stage and the inverted output terminal and the inverted output of the cascade. Go under slyucheny appropriately to the nerves. T-pinouts of the first and second capacitor terminals and the gates of the transistors are connected to the power supply terminal. The third fourth and fifth sixth transistors are added to the two additional capacitors, with each additional capacitor being connected to each other via a direct input ; and the output and the inverse input and output of the differential cascade “and the third and the core”; p tgzc li limpid tranz694: 32

Tyrs are connected in series and connected to the input signal buses, and the third and sixth and fifth transistors are connected to the paraphase control signal, and the connection points of the third and fourth, fifth and sixth transistors are connected respectively to the second terminals of the second and first capacitors

Fig. 1 shows the principle electric. The scheme of the proposed comparator on MIS transistors in FIG. 2 is a diagram of the control voltages of the input and output signals.

A comparator on MOS transistors contains a differential stage 1 | with direct and inverse inputs 2 3 and outputs 4 and 5, connected to the output buses 6 and 7 of the comparator, and between the direct input 2 and inverse output 5 and between the inverse I / O 3 direct output 4 includes switching transistors 8 and 9 of the feedback connection, the gates of which are connected to the control signal bus 10, while there are 5 inputs of the 2, 3 differential of the O of the cascade I to the points 11 "12 of the Connector :; ek podkggachen ler. to the second capacitors 13, 14, capacitors 5, 16 ,. and to the input buses 17,. 18 plug-in; successively connected third 19 to even ;; - dead 203 21 to sixth 22 transHCTOpbJs and third third i9 gates and sixth 22p fourth 20 and fifth 21 transistors connected to buses 23: 24 paraphase control sigal, respectively;

The diagrams for the directions in the comparator nodes. For example are shown in ftk, 2, Comparato .; Invet two modes of operation: n. and autocorrection-working mode: p, Zbkeki, Adjustment and Correspondence Correction Mode; high voltage level of the bus 0 control signal of the signal. At the same time, transis; 8 and. 9 in the feedback loop of the differential cascade: i and cr; you 5 a on. its inputs and outputs are set to approximately the same voltage level, corresponding to the operating point of the differential k.as s & j: i .s. I according to the constant com; yo The first plates of the decondenser 13 and 14 of the connection are connected.;: Output .5 and 4 differential cassettes 1, .a the second plates of the capacitors 13 and 14 through an open pair of transistors (for example, 20 21) connected to the input signal buses 7 and 18. Transistors 20 and 21 are open by a high level of switching para-phase signal on the bus 23. Transistors 19 and 22 are locked. In the setup and adjustment mode, capacitors 13 and 14 are charged to different values of the adapters, this difference is equal to the difference of voltages on the input buses 17, 18 of the comparator. When a low-level control signal appears on the bus 10, the feedback transistors 8 and 9 are locked. The comparator goes out of the adjustment and correction mode, but the voltage on the output buses 6 and 7 does not change, since the voltage on the inputs 2 and 3 of the differential stage 1 remains the same. The situation at the inputs and outputs of the differential stage 1 does not change with the appearance of a low voltage on the bus 23. This turns out to be locked transistors 19-22 With the appearance of a high voltage on the bus 24 unlocks the transistors 19, 22 and capacitors 13, 14 The connections are each connected to the comparator input, opposite to the one to which this capacitor was connected in the setup mode. Through the coupling capacitors 13 14, the voltage drop across the inputs 2 and 3 of the differential cascade 1 is equal to the voltage difference across the input buses and, in addition, the voltage difference to which the communication capacitors were charged in the configuration mode.

Thus, at the inputs 2 and 3 of the differential stage 1, the difference in the input voltages of the comparator doubles,

The gain of the comparator is determined not only by the sizes of the load and control transistors of the differential stage 1, but also by the ratio of the capacitors of the coupling capacitors to the parasitic interelectrode capacitances, and first of all the capacitive – t m gate – drain of the control transistors, since they are in the feedback loop of the differential stage. In addition, the gain of the differential stage is limited due to the non-linearity of the load transistors.

All of these limitations, inherent in the prototype and reducing the gain of the differential cascade, are eliminated by introducing the positive feedback capacitors 15 and 6 into the comparator. The capacitance of the capacitors 15,16 is chosen so that the capacitive positive feedback compensates for everything. negative feedback elements of the differential cascade.

The use in the comparator of the proposed switchboard input circuit will allow to double the gain and, consequently, improve the accuracy of the comparison. The introduction of compensating capacitors of positive feedback increases the gain by a factor of 3–4 without the risk of a trigger effect.

Claims (1)

COMPARATOR FOR MOSFET TRANSISTORS, containing a differential stage, two capacitors, two transistors, each of which is connected respectively between the direct input and the inverse output and between the inverse input and the direct output of the differential stage, the direct and inverse inputs of which are connected respectively to the first outputs of the first and second capacitors, and the gates of the transistors are connected to the bus of control signals, which is important in that, in order to increase accuracy by increasing the gain, the third, fourth, fifth, sixth transistors and two additional capacitors, with each additional capacitor connected respectively between the direct input and output and the inverse input and output of the differential stage, and the third and fourth, fifth and sixth transistors are connected in series and connected to the input buses signals, and the gates of the third and sixth, fourth and fifth transistors are connected respectively to the buses of the para-control signal, and the connection points of the third and fourth, fifth and sixth transistors are connected respectively to the second terminals of the second and first capacitors. 126943