JPS6484741A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6484741A
JPS6484741A JP24303587A JP24303587A JPS6484741A JP S6484741 A JPS6484741 A JP S6484741A JP 24303587 A JP24303587 A JP 24303587A JP 24303587 A JP24303587 A JP 24303587A JP S6484741 A JPS6484741 A JP S6484741A
Authority
JP
Japan
Prior art keywords
terminal electrodes
silicon
electrodes
reaction
highly concentrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24303587A
Other languages
Japanese (ja)
Other versions
JPH0581189B2 (en
Inventor
Shigeru Toyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24303587A priority Critical patent/JPS6484741A/en
Publication of JPS6484741A publication Critical patent/JPS6484741A/en
Publication of JPH0581189B2 publication Critical patent/JPH0581189B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To cope with the situation even when connection among a number of terminal electrodes is required and realize the formation of a bonding part having great bonding strength, by making the terminal electrodes equipped with metallic films where silicide can be formed on silicon added by highly concentrated impurities come closely into contact with the terminal electrodes, thereby treating the foregoing electrodes with heat. CONSTITUTION:Terminal electrodes 5 where silicon 3 added by highly concentrated impurities and films 4 consisting of metals which form silicide by acting thermally on silicon are laminated at a rate where excess silicon appears after reaction are formed on the first semiconductor substrate 1 and the terminal electrodes 9 consisting of metals which are the same kinds as the foregoing metal films have are formed on the second semiconductor substrate 6. Then alignment is performed by facing the first and second semiconductor substrates 1 and 6 each other and heat treatment is performed in a state that both electrodes 5 and 9 to be bonded come closely into contact with each other or are welded with pressure and then this approach allows the reaction of a solid phase silicide to take place between highly concentrated impurity-added silicon 3 and the metal films 4 of the terminal electrodes 5 and further allows its reaction to have an effect on the whole metal films of surfaces of the above silicon 3 and on a part or the whole terminal electrodes 9 and then performs connection between elements or devices.
JP24303587A 1987-09-28 1987-09-28 Manufacture of semiconductor device Granted JPS6484741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24303587A JPS6484741A (en) 1987-09-28 1987-09-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24303587A JPS6484741A (en) 1987-09-28 1987-09-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6484741A true JPS6484741A (en) 1989-03-30
JPH0581189B2 JPH0581189B2 (en) 1993-11-11

Family

ID=17097881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24303587A Granted JPS6484741A (en) 1987-09-28 1987-09-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6484741A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
US7959270B2 (en) 2005-12-23 2011-06-14 Xerox Corporation Collapsible packaging system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
US7959270B2 (en) 2005-12-23 2011-06-14 Xerox Corporation Collapsible packaging system

Also Published As

Publication number Publication date
JPH0581189B2 (en) 1993-11-11

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