JPS6484304A - Programmable controller - Google Patents

Programmable controller

Info

Publication number
JPS6484304A
JPS6484304A JP24206187A JP24206187A JPS6484304A JP S6484304 A JPS6484304 A JP S6484304A JP 24206187 A JP24206187 A JP 24206187A JP 24206187 A JP24206187 A JP 24206187A JP S6484304 A JPS6484304 A JP S6484304A
Authority
JP
Japan
Prior art keywords
program
circuit
ram
memory
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24206187A
Other languages
Japanese (ja)
Other versions
JP2613602B2 (en
Inventor
Masahiko Kitamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62242061A priority Critical patent/JP2613602B2/en
Publication of JPS6484304A publication Critical patent/JPS6484304A/en
Application granted granted Critical
Publication of JP2613602B2 publication Critical patent/JP2613602B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the load processing of a program by automatically selecting a RAM or a RAM in accordance with comparison between address data and a program area. CONSTITUTION:The titled device is constituted of a latch 8 to be a capacity setting circuit for storing the upper address of a program area corresponding to the capacity of a program, a memory selecting circuit 9 for selecting one of the RAM 2 and the ROM 3 as a program memory and outputting a selection signal corresponding to the selected memory, and address deciding circuit 7 for deciding whether address data are included in a program area or not in accordance with comparison between address data on an address bus AB and an upper address in the program area and outputting a deciding signal, and a memory switching circuit 4 for outputting a chip select signal, the inverse of CE to either one of the RAM 2 or the ROM 3 based on the selecting signal of the circuit 9 and the deciding signal of the circuit 7. Consequently, program loading processing to be generated by the switching of the program memory between the RAM 2 and and the ROM 3 can be reduced.
JP62242061A 1987-09-26 1987-09-26 Programmable controller Expired - Lifetime JP2613602B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242061A JP2613602B2 (en) 1987-09-26 1987-09-26 Programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242061A JP2613602B2 (en) 1987-09-26 1987-09-26 Programmable controller

Publications (2)

Publication Number Publication Date
JPS6484304A true JPS6484304A (en) 1989-03-29
JP2613602B2 JP2613602B2 (en) 1997-05-28

Family

ID=17083700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242061A Expired - Lifetime JP2613602B2 (en) 1987-09-26 1987-09-26 Programmable controller

Country Status (1)

Country Link
JP (1) JP2613602B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107591A (en) * 1984-10-31 1986-05-26 Toshiba Corp Memory select control circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107591A (en) * 1984-10-31 1986-05-26 Toshiba Corp Memory select control circuit

Also Published As

Publication number Publication date
JP2613602B2 (en) 1997-05-28

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