JPS61107591A - Memory select control circuit - Google Patents

Abstract

PURPOSE:To cope with the change of a memory structure without changing the hardware configuration by setting a chip select signal to be supplied programmably to the ROM/RAM memory. CONSTITUTION:Output from comparator 14 holds '1' for upper 4 bits in an address bus 3 from 0 through 3, and holds '0' when the address bus 3 is in a range from 4 through F. Therefore, a chip select signal CS0 holds '1' when the upper 4 bits of the address bus 3 are in a range from the bit 0 through the bit 3 and holds '0' when the upper 4 bits of the address bus 3 are in a range from the bit 4 through a bit F. A RAM5 is accessed while a chip select signal CS0 holds '1', or when the address bus 3 is in a range from '00000' (HEX) to '3FFFF' (HEX). The output from a comparator 15 holds '1' when the upper 4 bits of the address bus 3 are in a range from 0 to 7, and holds '0' for a range from 8 to F. As a chip select signal CS1 is the output from gate 19, the signal CS1 holds '1' when an output from a comparator 14 holds '0' and an output from comparator 15 holds '1', that is, when the upper 4 bits of the address bus 3 are in a range from 4 to 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory selection control circuit that can flexibly cope with changes in memory configuration.

[Technical background of the invention and its problems]

A chip select signal for an IC memory such as a general FI, ROM, or RAM is generated by decoding an address signal using hardware.

However, since the hardware is designed only for a specific memory configuration, it cannot keep up with changes in the memory configuration. In other words, the hardware must be redesigned.

In particular, when incorporating a decoding circuit into an r-) array (hereinafter referred to as GA), if the decoding circuit is designed only for a specific memory configuration, if the memory configuration is changed, the GA external This required a decoding circuit to be created, which was disadvantageous in terms of cost. Furthermore, it is not practical in terms of cost and delivery time to redesign the KGA every time the memory configuration is changed.

In actual GA, it may be possible to switch so that only several types of memory configurations can be supported. However, when a memory configuration other than that previously considered is required, the problem is similar to that described above, and there is still the inconvenience that a decoding circuit must be created outside the GA.

[Purpose of the invention]

The present invention has been made in view of the above drawbacks, and the present invention has been made in view of the above-mentioned drawbacks.
It is an object of the present invention to provide a memory selection control circuit that can programmably set a chip select signal to be supplied to a RAM memory, and in particular can cope with changes in memory configuration without changing hardware.

[Summary of the invention]

In order to achieve the above object, the present invention adds a register, a converter, and a dart to each step constituting the memory. Data for chip select signal control according to the memory configuration is set in the above register when the system is initialized, and this data and a part of the address signal commonly supplied to each chip are individually set by the above comparator. be compared. Then, the conditions for each connogulator output are determined by the dart, and an optimum chip select signal is supplied to each memory chip according to the memory configuration.

This makes it possible to respond more flexibly to changes in memory configuration without requiring any changes to the hardware.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1 is a CPU serving as a control center. 2 is 8
3 is a 20-bit address bus, with AO being the LSB.

A1. indicates the MSB. 4 is ROM (R@ad On
lyMemory) and the address is 'F'ooo
641 from “σ” (awx) to “FFFFP” (mix)
It is fixed at cB (kilopite). 5, 6, 7.
8 is RAM (Random Memory
The capacity of one RAM □,1 is 64 kB or 256 kB, and is programmable from a total of OkB to 960 kB. 9 is an address bus, and the lower 18 of the above address bus 3
bits, AO to A+v.

Reference numerals 10, 11 and 12, 13 are registers each having a 4-pit configuration, in which data for controlling the chip select signal of the RAM is stored. When the system is initialized, data is set by the CPU IK, and all are @O" at the time of initialization.1
4, 15, 16° 17 are Konno 9 rators. Each controller has the upper 4 bits of the address bus 3, i.e.
From ASS to A+ and each register 10, 11, 12, 13
The data placed in is supplied. What are the results compared here? ' - is supplied to ports 19, 20, and 21. 'r'-
19, 20.21 are the above-mentioned conno arm levers 14, 15,
16. Taking the output conditions of 17, each RAM 5, 5
, 7, and 8 chip select signals are generated.

The operation of one embodiment of the present invention will be explained in detail below. First, when the system is started, the CPU 1 starts executing the program on the ROM 4. At this stage, the initial value "0" is set in registers 10, 11, 12.13. Therefore, each comparator 14.15, 16.17 output will never be 1" for any address, and therefore each chip select signal (CSo - CS
s ) will also never be '1'.

That is, each RAM 5, 6, 7, and 8 is not accessed ~1 degree. Furthermore, prior to operation, the program on ROM n is
Before accessing M 5 , 6 , 7 , and 8 , data determined by the memory configuration is set in each register 10 , 11 , 12 , and 13 . Here, two types of memory configurations will be illustrated and explained. Each,! This is shown as a timing chart in Fig. Jc2 and Fig. 3. The first memory configuration is each RAM 5, 6, 7, and 8 is 256
kB. However, RAM 8 is 256
192kB of the kB is used. In this case, register 10
4”.

The register 1 is set to 11811, the register 12 is set to "C", and the register 13 is set to "F". In the figure, it is surrounded by a 0 frame. At this time, the output of the controller 14 becomes "I" while the upper 4 bits of the address bus 3 are from O to 3.
The chip select signal C8o is 10'' from 4 to F. Therefore, the chip select signal C8o is 1'' when the upper 4 bits of the address bus 3 are from O to 3, and 0 from 4 to F''1.
becomes. RAM 5 receives a chip select signal cSo
7! l"1", that is, address bus 3 is 1lOO
OOOIl (□x) to 3FFFF” (wax) 1. The output of the controller 7 and the regulator 15 is ``1'' when the upper 4 bits of the address bus 3 are from 0 to 7, and from 8 to Ft. Since it is the output of the chip select signal CS I+ff-to 19, the output of the comparator 15 is ``0'' when the comparator output is ``0''.
l'' time.

That is, the upper four bits of address bus 3 become ``1'' only from 4 to 7.

For RAM 6, when the chip select signal cs is 1″0,
In other words, address bus 3 starts from '40000' (izx) @
7FF'FF'' (gzx).The output of the comparator 16 is ``1'' when the upper 4 bits of the address bus 3 are from 0 to B, and from C to Ft@
0".Chip select signal C8, ba, dirt 20
Therefore, when the output of the comparator 15 is θ'' and the output of the comparator 16 is '1', that is, the address bus 3
The upper 4 bits of are "1" only between 8 and Bt.

While the chip select signal C83 is 1″, the RAM 7
In other words, address bus 3 starts from "80000" (izx).
BF'FFF''' (ggx) is accessed. The output of the comparator 17 is ``1'' when the upper 4 bits of the address bus 3 are from O to it, and becomes ``0'' when it is F.

Since the chip select signal C8s is the output of the gate 21, when the output of the comparator 16 is "O" and the output of the comparator 17 is "1", that is.

The upper 4 bits of address bus 3 are between C and Et.
It becomes "l". RAM & is chip select signal C8
While s is @1m, that is, address bus 3 is “C00O
O” (mmx) to □1”EFF
FF" (IIIX) t. According to this memory configuration example, the total RAM capacity is 960 kB.

The operation of another example memory configuration is shown in FIG. In this example, RAM 5 is 256 kB.

RAM 6 is 64kB, and RAM 7.8 is not installed. In this case, register 1σ is set to ``4'', register 1 is set to ``5'', register 12 is set to ``0'', and register 13) is set to ``O''. The output of the comparator 14 is "1" when the upper 4 bits of the address bus 3 are from O to 3, and "O" from 4 to F. Therefore, the chip select signal C8 is the address The upper 4 bits of bus 3 are 1'' from 0 to 3.

While the chip select signal C8o is 'l', the RAM 5
That is, the address bus 3 is accessed from @ooooo'' (imz) to '3FFFFF'' (Hzx).

The output of the router 15 is "1" when the upper four bits of the address bus 3 are from 0 to 4, and is "0" from 5 to F. Chip select signal C8t is gate 1
Since the output of core /4' is "0" and the output of comparator 15 is "1", that is, when the upper 4 bits of address bus 3 are "4",
1''.RAM 6 is chip select signal C8s
is 1", that is, the address bus 3 changes from '40000' (Hxx) to '4F'FFF" (H
mx) is accessed. Here, since the capacity of RAM 6 is 64 kB, the address bus 18 of RAM 6 is
Among the pits, the lower 16 bits AO to A151 are used, and the upper 2 bits A16 and A17 are not used. Here, the outputs of the comparators 16 and 17 do not become "1". Therefore, gate 20. ;CSt which is the output of 21.

C8, is also not output, and RAMs 7 and 8 are never accessed. According to the example memory configuration, the total RAM capacity is 320 kB.

Incidentally, in the embodiments of the present invention, only the case where the memory is constituted by RAM has been described, but the present invention can be applied in exactly the same way even if the memory is constituted by ROM. However, in the case of a ROM, it is necessary to design a ROM that stores a program that is accessed at system startup so that it can be accessed at all times.

〔Effect of the invention〕

As described above, the present invention provides the following effects.

(1) If the memory configuration changes, it can be handled simply by changing the software without changing the hardware.

(2) If a decoding circuit is included in the GA, the G
Since the versatility of A is improved, the cost and time of developing a new GA can be saved.

(3) Compatible with various memory configurations. That is, it is possible to use part of the memory capacity of a memory configuration in which memories of different capacities coexist, and to cope with large capacity memories that will appear in the future.

[Brief Description of the Drawings] Figure 1 is a block diagram showing an embodiment of the present invention, Figures 2 and 3 are block diagrams showing an embodiment of the present invention.
The figure is a timing chart showing the operation of the embodiment of the present invention. 1...CPU, 4...ROM, 5, 6, 7.8...
・RAM. 10.11, 12.13...Register, 14°15.
16.11...Hun/J? rater, 19,20゜21
···dirt. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2rA C53t

Claims (1)

[Claims] A memory composed of multiple memory chips and a memory that is constantly accessed separately from this memory, depending on the above memory configuration,
A ROM that stores a program that sets data for controlling a chip select signal supplied to each memory chip, and a register that is provided corresponding to each of the memory chips and in which the data is set under the control of a CPU. , a plurality of comparators that compare the individual values set in this register with part of the address information commonly given by the CPU, and a chip select signal to each of the above memory chips based on the conditions of the comparator output. 1. A memory selection control circuit comprising: a gate for supplying a signal.