JPS64822A - Error correcting circuit - Google Patents

Error correcting circuit

Info

Publication number
JPS64822A
JPS64822A JP14728787A JP14728787A JPS64822A JP S64822 A JPS64822 A JP S64822A JP 14728787 A JP14728787 A JP 14728787A JP 14728787 A JP14728787 A JP 14728787A JP S64822 A JPS64822 A JP S64822A
Authority
JP
Japan
Prior art keywords
error
bit position
decoder
sequences
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14728787A
Other languages
Japanese (ja)
Other versions
JPH01822A (en
Inventor
Hidetoshi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62-147287A priority Critical patent/JPH01822A/en
Priority claimed from JP62-147287A external-priority patent/JPH01822A/en
Publication of JPS64822A publication Critical patent/JPS64822A/en
Publication of JPH01822A publication Critical patent/JPH01822A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To miniaturize a device and to quickly perform the operation by detecting an error sequence and an error bit position by a decoder consisting of plural gate circuits.
CONSTITUTION: An error sequence decoder 31 turns on outputs corresponding to three sequences a1∼a3 to send error sequence information to a correcting part 14. An error bit decoder turns on the output corresponding to a code length to send error bit position information to a shift register 50. The register 50 and a delay part 13 synchronize parallel data DPH of three sequences, where error is detected on the basis of a prescribed clock CLK, in bit position units. Error is detected in ANDs 14a∼14c of the correcting part 14 in accordance with error sequence information and error bit position information, and error is corrected to exclusive ORs 14d∼14f, and parallel data DPH, after error correction is sent.
COPYRIGHT: (C)1989,JPO&Japio
JP62-147287A 1987-06-12 error correction circuit Pending JPH01822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-147287A JPH01822A (en) 1987-06-12 error correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-147287A JPH01822A (en) 1987-06-12 error correction circuit

Publications (2)

Publication Number Publication Date
JPS64822A true JPS64822A (en) 1989-01-05
JPH01822A JPH01822A (en) 1989-01-05

Family

ID=

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6276856B1 (en) 1999-01-12 2001-08-21 The Procter & Gamble Company Self cleaning dip-in package for liquids

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6276856B1 (en) 1999-01-12 2001-08-21 The Procter & Gamble Company Self cleaning dip-in package for liquids

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