JPS6479835A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6479835A
JPS6479835A JP62236168A JP23616887A JPS6479835A JP S6479835 A JPS6479835 A JP S6479835A JP 62236168 A JP62236168 A JP 62236168A JP 23616887 A JP23616887 A JP 23616887A JP S6479835 A JPS6479835 A JP S6479835A
Authority
JP
Japan
Prior art keywords
processor
diagnosis
control
fault
adapter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62236168A
Other languages
Japanese (ja)
Inventor
Hajime Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62236168A priority Critical patent/JPS6479835A/en
Publication of JPS6479835A publication Critical patent/JPS6479835A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To allow a diagnosis processor to inform a fault to an input/output (I/O) control processor in stead of an I/O control adapter through a diagnosis bus by allowing the diagnosis processor to execute fault detection in the I/O control adapter and fault information to the I/O control processor through the diagnosis bus. CONSTITUTION:When a hardware error is generated during the operation of a microprogram routine in the I/O control adapter (ADP) 10A, e.g., an error detecting circuit 19 requests a status register 20 to set up error status relating to the disableness of a microprogram. As the result, a diagnosis bus control part 17 recognizes a fatal error generation in the register 20, adds an adapter discriminator and interrupts a diagnosis bus control part 23 is a dignosis processor (DGP) 4. As the result, the DGP 4 identifies the interruption and informs the identified result to an I/O instruction processor (IOP) 8, so that fault information to an operation processor (EPU) 1 and software (monitoring program) can be attained and the system can be prevented from generating an important fault.
JP62236168A 1987-09-22 1987-09-22 Data processor Pending JPS6479835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62236168A JPS6479835A (en) 1987-09-22 1987-09-22 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62236168A JPS6479835A (en) 1987-09-22 1987-09-22 Data processor

Publications (1)

Publication Number Publication Date
JPS6479835A true JPS6479835A (en) 1989-03-24

Family

ID=16996778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62236168A Pending JPS6479835A (en) 1987-09-22 1987-09-22 Data processor

Country Status (1)

Country Link
JP (1) JPS6479835A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10146935A1 (en) * 2001-09-24 2003-04-17 Infineon Technologies Ag Processing of photolithographic reticle for integrated circuit, involves passing specific gas to chamber having reticle with photomask and patterned resist, generating plasma and removing exposed portions of photomask
JPWO2012172682A1 (en) * 2011-06-17 2015-02-23 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10146935A1 (en) * 2001-09-24 2003-04-17 Infineon Technologies Ag Processing of photolithographic reticle for integrated circuit, involves passing specific gas to chamber having reticle with photomask and patterned resist, generating plasma and removing exposed portions of photomask
JPWO2012172682A1 (en) * 2011-06-17 2015-02-23 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device

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