JPS6478544A - Network synchronizing device - Google Patents
Network synchronizing deviceInfo
- Publication number
- JPS6478544A JPS6478544A JP62236702A JP23670287A JPS6478544A JP S6478544 A JPS6478544 A JP S6478544A JP 62236702 A JP62236702 A JP 62236702A JP 23670287 A JP23670287 A JP 23670287A JP S6478544 A JPS6478544 A JP S6478544A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- station
- synchronized
- order
- hierarchical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To prevent an error from occurring in the communication between most stations by selecting a clock synchornized with the most significant clock of the hierarchy when a clock form a high-order station is not received, and making the network synchronized with said clock. CONSTITUTION:In case a clock to be transmitted to the low-order station is synchronized with that of the high-order station, a synchronized clock oscillation circuit 1 inserts the hierarchical number of the synchronized station by its inserting means 6, then transmits the clock. In case of not receiving the clock of the high-order station, the hierarchical number of the self station is read out from a memory means, and the number is inserted by the means 6 and then transmitted. In the low-order station, the hierarchical numbers are extracted by extraction means 3, 4 from the clocks inputted from the plural high-order stations, so that a selection means 5 selects the clock in the hierarchical number of the station in the most significant station of the extracted numbers. The selected clock is transmitted to the circuit 1 to synchronize the circuit 1 with it. As a result, even if a clock signal can not be received, the self station can be synchronized with a clock synchronized with the clock in the most significant clock of the hierarchical numbers among the clocks inputted from the plural high-order stations.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62236702A JPS6478544A (en) | 1987-09-21 | 1987-09-21 | Network synchronizing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62236702A JPS6478544A (en) | 1987-09-21 | 1987-09-21 | Network synchronizing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6478544A true JPS6478544A (en) | 1989-03-24 |
Family
ID=17004499
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62236702A Pending JPS6478544A (en) | 1987-09-21 | 1987-09-21 | Network synchronizing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6478544A (en) |
-
1987
- 1987-09-21 JP JP62236702A patent/JPS6478544A/en active Pending
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