JPS6476761A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6476761A
JPS6476761A JP23228887A JP23228887A JPS6476761A JP S6476761 A JPS6476761 A JP S6476761A JP 23228887 A JP23228887 A JP 23228887A JP 23228887 A JP23228887 A JP 23228887A JP S6476761 A JPS6476761 A JP S6476761A
Authority
JP
Japan
Prior art keywords
etching
metal layer
emitter
base
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23228887A
Other languages
Japanese (ja)
Other versions
JP2579952B2 (en
Inventor
Kohei Moritsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62232288A priority Critical patent/JP2579952B2/en
Publication of JPS6476761A publication Critical patent/JPS6476761A/en
Priority to US07/584,443 priority patent/US5124270A/en
Application granted granted Critical
Publication of JP2579952B2 publication Critical patent/JP2579952B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To enable easy manufacturing and high speed operation, by constituting a metal layer of a first metal layer which has almost the same size with the base region width of an intrinsic transistor region, and a second metal layer, formed thereon, having a width larger than that of the first metal layer. CONSTITUTION:On the whole surface of a wafer, molibudenum 10 is formed, and thereon an emitter electrode pattern of gold 11 is formed by a lift-off method. By using this gold as a mask, the molybdenum is subjected to reactive ion etching in which a mixed gas of CF4O2 is used, and eliminated. By over- etching, the molybdenum layer 10 in subjected to side-etching. Since a base electrode 13 and an emitter region 5 are isolated, the direction of an emitter stripe can be freely set. After a base electrode pattern is formed by using a photo resist 12, emitter semiconductor layers 7, 6, 5 are eliminated by etching, and a base layer 4 is exposed. Abnormal etching which is apt to occur on the boundary surface between AuGe and GaAs does not occur, and sufficient reproducibility is obtained.
JP62232288A 1987-09-18 1987-09-18 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2579952B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62232288A JP2579952B2 (en) 1987-09-18 1987-09-18 Semiconductor device and manufacturing method thereof
US07/584,443 US5124270A (en) 1987-09-18 1990-09-17 Bipolar transistor having external base region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62232288A JP2579952B2 (en) 1987-09-18 1987-09-18 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS6476761A true JPS6476761A (en) 1989-03-22
JP2579952B2 JP2579952B2 (en) 1997-02-12

Family

ID=16936868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62232288A Expired - Fee Related JP2579952B2 (en) 1987-09-18 1987-09-18 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2579952B2 (en)

Also Published As

Publication number Publication date
JP2579952B2 (en) 1997-02-12

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees