JPS6476249A - Command synchronization establishing circuit - Google Patents
Command synchronization establishing circuitInfo
- Publication number
- JPS6476249A JPS6476249A JP23409387A JP23409387A JPS6476249A JP S6476249 A JPS6476249 A JP S6476249A JP 23409387 A JP23409387 A JP 23409387A JP 23409387 A JP23409387 A JP 23409387A JP S6476249 A JPS6476249 A JP S6476249A
- Authority
- JP
- Japan
- Prior art keywords
- control device
- command
- transmitting
- establishing circuit
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To execute the synchronization establishment of a transmitting and receiving command by storing the ending condition of the transmitting and receiving command on a common bus interface with a command synchronization establishing circuit and informing of it in correspondence to an access from a main body device. CONSTITUTION:A main device 1 has a central control device, a main memory to be connected to this control device and a channel device to be connected to the central control device in duplex constitution. An input and output control device 3 is connected through these channel devices and a common bus interface 2 and the reception of data from a line and the transmission of the data of the main memory are executed by DMA operation with being not-synchronized. In this input and output control device 3, a command synchronization establishing circuit 4 is provided and the ending condition of the transmitting and receiving command on the interface 2 is stored and informed an input and output control device firmware according to the access from the device 1. Thus, the synchronization of the command can be obtained between the device 1 and the device 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23409387A JPH0758481B2 (en) | 1987-09-18 | 1987-09-18 | Command matching establishment circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23409387A JPH0758481B2 (en) | 1987-09-18 | 1987-09-18 | Command matching establishment circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6476249A true JPS6476249A (en) | 1989-03-22 |
JPH0758481B2 JPH0758481B2 (en) | 1995-06-21 |
Family
ID=16965508
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23409387A Expired - Lifetime JPH0758481B2 (en) | 1987-09-18 | 1987-09-18 | Command matching establishment circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0758481B2 (en) |
-
1987
- 1987-09-18 JP JP23409387A patent/JPH0758481B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0758481B2 (en) | 1995-06-21 |
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