JPS6421618A - Electronic equipment - Google Patents

Electronic equipment

Info

Publication number
JPS6421618A
JPS6421618A JP17838687A JP17838687A JPS6421618A JP S6421618 A JPS6421618 A JP S6421618A JP 17838687 A JP17838687 A JP 17838687A JP 17838687 A JP17838687 A JP 17838687A JP S6421618 A JPS6421618 A JP S6421618A
Authority
JP
Japan
Prior art keywords
power supply
buffer
unit
reception
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17838687A
Other languages
Japanese (ja)
Inventor
Toru Kosaka
Hiroyuki Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17838687A priority Critical patent/JPS6421618A/en
Publication of JPS6421618A publication Critical patent/JPS6421618A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bidirectional Digital Transmission (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To miniaturize the device by providing a main body operating each electric equipment unit by its own power supply, a buffer operated by its own or other unit power supply and sending/receiving a data with a common bus to the main body and a control means applying only the reception at the stop of its own power supply. CONSTITUTION:A buffer 22a of a unit 1a consists of a unidirectional amplifier 23a formed by a logic IC, a signal of a bus 2 is sent to the main body and the power is supplied via a diode circuit 18 and only the reception is applied from the bus 2 even when its own power supply 15 is stopped. A unidirectional amplifier is connected inversely in parallel with the buffer 22b of the unit 1b and an inverter circuit 25b controls the buffer and the transmission only is attained at the operation of the power supply and at the power interruption, the reception only is attained. In the unit 1n, a bidirectional buffer 22n is controlled by an inverter circuit 25n and only the reception is applied from the bus 2 at power supply interruption similarly in case of the units 1a, 1b. By such a constitution, the communication signals for the units are isolated electrically and the size is miniaturized.
JP17838687A 1987-07-17 1987-07-17 Electronic equipment Pending JPS6421618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17838687A JPS6421618A (en) 1987-07-17 1987-07-17 Electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17838687A JPS6421618A (en) 1987-07-17 1987-07-17 Electronic equipment

Publications (1)

Publication Number Publication Date
JPS6421618A true JPS6421618A (en) 1989-01-25

Family

ID=16047583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17838687A Pending JPS6421618A (en) 1987-07-17 1987-07-17 Electronic equipment

Country Status (1)

Country Link
JP (1) JPS6421618A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5249857A (en) * 1989-10-30 1993-10-05 Kyoraku Co., Ltd. Built-up furniture unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5249857A (en) * 1989-10-30 1993-10-05 Kyoraku Co., Ltd. Built-up furniture unit

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