JPS57184353A - Communication controller - Google Patents

Communication controller

Info

Publication number
JPS57184353A
JPS57184353A JP56070016A JP7001681A JPS57184353A JP S57184353 A JPS57184353 A JP S57184353A JP 56070016 A JP56070016 A JP 56070016A JP 7001681 A JP7001681 A JP 7001681A JP S57184353 A JPS57184353 A JP S57184353A
Authority
JP
Japan
Prior art keywords
data
signal
cpu
memory
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56070016A
Other languages
Japanese (ja)
Inventor
Hideaki Oota
Kenichi Teramoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP56070016A priority Critical patent/JPS57184353A/en
Publication of JPS57184353A publication Critical patent/JPS57184353A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Abstract

PURPOSE:To prevent the deterioration of the service time of a CPU to the process when the speed of communication is increased, by storing previously the data to be transmitted or the redeived data in a buffer memory and then transmitting or reading successively these data. CONSTITUTION:In the case of transmission of the data, a CPU sets the transmitting data to a buffer memory 7 and then transmits the transmission start signal. Receiving this signal, an asynchronous receiver/transmitter ART9 transmits the data set at the memory 7 to the remote side through a terminal TRO. Then the circuit is switched to a reception mode when the transmission end signal is transmitted. Thus the ART9 receives the signal from the remote side through a terminal Ri to successively store the signal in the memory 7. When the reception end signal is received, the data of the memory 7 is transferred to the CPU through a gate circuit 8 and a data bus 4 and under the control of the CPU.
JP56070016A 1981-05-09 1981-05-09 Communication controller Pending JPS57184353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56070016A JPS57184353A (en) 1981-05-09 1981-05-09 Communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56070016A JPS57184353A (en) 1981-05-09 1981-05-09 Communication controller

Publications (1)

Publication Number Publication Date
JPS57184353A true JPS57184353A (en) 1982-11-13

Family

ID=13419386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56070016A Pending JPS57184353A (en) 1981-05-09 1981-05-09 Communication controller

Country Status (1)

Country Link
JP (1) JPS57184353A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51100653A (en) * 1975-03-04 1976-09-06 Nippon Telegraph & Telephone
JPS51135303A (en) * 1975-05-20 1976-11-24 Nippon Telegr & Teleph Corp <Ntt> Transmission reception mode switching block

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51100653A (en) * 1975-03-04 1976-09-06 Nippon Telegraph & Telephone
JPS51135303A (en) * 1975-05-20 1976-11-24 Nippon Telegr & Teleph Corp <Ntt> Transmission reception mode switching block

Similar Documents

Publication Publication Date Title
JPS6453253A (en) External apparatus connected to digital data processing system
JPS6477339A (en) Collision detecting type lan terminal interface module
ES474858A1 (en) Directional coupler
JPS5617563A (en) Facsimile storing and converting device
JPS5592068A (en) Voice data composite communication system
JPS5573157A (en) Data communication system
JPS57184353A (en) Communication controller
JPS574653A (en) Transmitting system of facsimile picture information
EP0315549A3 (en) Protocol control circuit for data bus system
JPS5739646A (en) Interruption controlling system during communication
JPS56123131A (en) Radio repeater
JPS5621443A (en) Transmission unit
JPS5630347A (en) Single-speed digital subscriber&#39;s line transmission system
JPS6481544A (en) Plural type cdt system using one radio wave
JPS5624867A (en) Facsimile simultaneous transmission and reception system
JPS57113664A (en) Display system for communication management
JPS5715550A (en) Data transmission system
JPS5661865A (en) Facsimile communication system
JPS6474868A (en) Facsimile equipment
JPS57178447A (en) Loop data transmission system
JPS575453A (en) Nonaudio processing system for digital audio
JPS6429041A (en) Data transmission reception controller
JPS54159101A (en) Communication control unit
JPS56132840A (en) Method and equipment for transmission control
JPS5664549A (en) Message transmission control system