JPS6473811A - Schmitt circuit - Google Patents

Schmitt circuit

Info

Publication number
JPS6473811A
JPS6473811A JP23026087A JP23026087A JPS6473811A JP S6473811 A JPS6473811 A JP S6473811A JP 23026087 A JP23026087 A JP 23026087A JP 23026087 A JP23026087 A JP 23026087A JP S6473811 A JPS6473811 A JP S6473811A
Authority
JP
Japan
Prior art keywords
circuit
cmos
cmos circuit
bipolar
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23026087A
Other languages
Japanese (ja)
Inventor
Isao Matsumoto
Hiroyuki Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23026087A priority Critical patent/JPS6473811A/en
Publication of JPS6473811A publication Critical patent/JPS6473811A/en
Pending legal-status Critical Current

Links

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  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To realize a fast operation and low power consumption, by forming a BiCMOS circuit constituted by combining a bipolar transistor circuit and three sets of CMOS circuits and providing a hysteresis characteristic. CONSTITUTION:The said circuit is provided with a first CMOS circuit of P1 and N1, a second CMOS circuit of P3 and N3, a third CMOS circuit (P4 and N4), and the bipolar circuit (Q1 and Q2). The hysteresis characteristic is attached on the first CMOS circuit (P1 and N1) by varying apparent resistance values of a first resistor R1 and a third resistor R3, respectively, provided at the first CMOS circuit (P1 and N1) by the second CMOS circuit (P4 and N3) and the third third CMOS circuit. The low power consumpition is realized in those CMOS circuits (P1 and N1), (P3 and N3), and (P4 and N4), respectively. The output of the first CMOS circuit (P1 and N1) is outputted from the bipolar circuit (Q1 and Q2), and the fast operation is performed by applying large current driving on a load.
JP23026087A 1987-09-14 1987-09-14 Schmitt circuit Pending JPS6473811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23026087A JPS6473811A (en) 1987-09-14 1987-09-14 Schmitt circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23026087A JPS6473811A (en) 1987-09-14 1987-09-14 Schmitt circuit

Publications (1)

Publication Number Publication Date
JPS6473811A true JPS6473811A (en) 1989-03-20

Family

ID=16905015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23026087A Pending JPS6473811A (en) 1987-09-14 1987-09-14 Schmitt circuit

Country Status (1)

Country Link
JP (1) JPS6473811A (en)

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