JPS6472122A - Electrooptic device using tft array - Google Patents

Electrooptic device using tft array

Info

Publication number
JPS6472122A
JPS6472122A JP22817887A JP22817887A JPS6472122A JP S6472122 A JPS6472122 A JP S6472122A JP 22817887 A JP22817887 A JP 22817887A JP 22817887 A JP22817887 A JP 22817887A JP S6472122 A JPS6472122 A JP S6472122A
Authority
JP
Japan
Prior art keywords
gate line
stage
current
last
holding capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22817887A
Other languages
Japanese (ja)
Inventor
Hiroshi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP22817887A priority Critical patent/JPS6472122A/en
Publication of JPS6472122A publication Critical patent/JPS6472122A/en
Pending legal-status Critical Current

Links

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  • Liquid Crystal (AREA)

Abstract

PURPOSE:To prevent an abnormal voltage from being applied to the holding capacitor of a current stage and to improve the display quality by applying a gate pulse to the gate line of the current stage after a time constant determined by at least the resistance and capacity of the gate line of the last stage. CONSTITUTION:The current stage gate pulse 11 is applied to the current stage gate line 3 after time is elapsed by the time constant tau determined by the capacity of the last-stage gate line 2. Thus, the TFT array is driven to write a signal in the holding capacitor 5 by the TFT 7 on the current-stage gate line 3 in an area where variation in the transient variation of the last-stage gate line 3 is sufficiently small. Consequently, an abnormal voltage is prevented from being applied to the holding capacitor 5 to improve the display quality.
JP22817887A 1987-09-11 1987-09-11 Electrooptic device using tft array Pending JPS6472122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22817887A JPS6472122A (en) 1987-09-11 1987-09-11 Electrooptic device using tft array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22817887A JPS6472122A (en) 1987-09-11 1987-09-11 Electrooptic device using tft array

Publications (1)

Publication Number Publication Date
JPS6472122A true JPS6472122A (en) 1989-03-17

Family

ID=16872436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22817887A Pending JPS6472122A (en) 1987-09-11 1987-09-11 Electrooptic device using tft array

Country Status (1)

Country Link
JP (1) JPS6472122A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63118128A (en) * 1986-11-05 1988-05-23 Oki Electric Ind Co Ltd Driving method for active matrix type liquid crystal display device
JPS6460161A (en) * 1987-08-31 1989-03-07 Matsushita Electric Ind Co Ltd Method for driving active matrix liquid crystal panel

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63118128A (en) * 1986-11-05 1988-05-23 Oki Electric Ind Co Ltd Driving method for active matrix type liquid crystal display device
JPS6460161A (en) * 1987-08-31 1989-03-07 Matsushita Electric Ind Co Ltd Method for driving active matrix liquid crystal panel

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