JPS647151A - Bus acquisition system - Google Patents

Bus acquisition system

Info

Publication number
JPS647151A
JPS647151A JP16096487A JP16096487A JPS647151A JP S647151 A JPS647151 A JP S647151A JP 16096487 A JP16096487 A JP 16096487A JP 16096487 A JP16096487 A JP 16096487A JP S647151 A JPS647151 A JP S647151A
Authority
JP
Japan
Prior art keywords
bus
signal
control circuit
latch
order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16096487A
Other languages
Japanese (ja)
Inventor
Tsuneo Fujiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16096487A priority Critical patent/JPS647151A/en
Publication of JPS647151A publication Critical patent/JPS647151A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To give the bus use right even to a user device having a low priority level which first requests the bus use, by providing a bus controller with a user device priority level discriminating circuit and a bus request order storage circuit. CONSTITUTION:When urgently requesting the bus use, a user device 40 sets a latch request signal 403 to logical '1' and sends this signal to a latch control circuit 11. When receiving this latch request signal 403, the latch control circuit 11 sends a control signal 011 to a storage control circuit 13. Numbers of user devices are stored in the storage control circuit 13 in the order of sending of the bus request signal. Consequently, the storage control circuit 13 sends a bus acknowledge signal to user devices in the order of sending of the bus request signal on the basis of the control signal 011. That is, the bus use right is given to user devices in the request order.
JP16096487A 1987-06-30 1987-06-30 Bus acquisition system Pending JPS647151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16096487A JPS647151A (en) 1987-06-30 1987-06-30 Bus acquisition system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16096487A JPS647151A (en) 1987-06-30 1987-06-30 Bus acquisition system

Publications (1)

Publication Number Publication Date
JPS647151A true JPS647151A (en) 1989-01-11

Family

ID=15725982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16096487A Pending JPS647151A (en) 1987-06-30 1987-06-30 Bus acquisition system

Country Status (1)

Country Link
JP (1) JPS647151A (en)

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