JPS647152A - Bus controller - Google Patents

Bus controller

Info

Publication number
JPS647152A
JPS647152A JP16096387A JP16096387A JPS647152A JP S647152 A JPS647152 A JP S647152A JP 16096387 A JP16096387 A JP 16096387A JP 16096387 A JP16096387 A JP 16096387A JP S647152 A JPS647152 A JP S647152A
Authority
JP
Japan
Prior art keywords
bus
user devices
logical
bus request
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16096387A
Other languages
Japanese (ja)
Inventor
Tsuneo Fujiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16096387A priority Critical patent/JPS647152A/en
Publication of JPS647152A publication Critical patent/JPS647152A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To certainly give the bus use right to a user device having a low priority level after a prescribed period by monitoring user devices, which cannot practically use the bus for the prescribed period, by a bus request monitor control circuit. CONSTITUTION:A bus request monitor control circuit 11 uses a control signal 011 to monitor bus request signals of user devices 20, 30, and 40 and detects user devices which cannot use a buss 051 for the prescribed time after one of bus request signals of user devices 20, 30, and 40 goes to logical '1'. As the result, a storage control circuit 13 is so instructed for the prescribed period that user devices are permitted to use the bus 051 in the order of going to logical '1' of bus request signals. This storage control circuit 13 sets bus acknowledge signals to user devices to logical '1' in the order of going to logical '1' of bus request signals.
JP16096387A 1987-06-30 1987-06-30 Bus controller Pending JPS647152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16096387A JPS647152A (en) 1987-06-30 1987-06-30 Bus controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16096387A JPS647152A (en) 1987-06-30 1987-06-30 Bus controller

Publications (1)

Publication Number Publication Date
JPS647152A true JPS647152A (en) 1989-01-11

Family

ID=15725962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16096387A Pending JPS647152A (en) 1987-06-30 1987-06-30 Bus controller

Country Status (1)

Country Link
JP (1) JPS647152A (en)

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