JPS6471351A - Digital phase locked loop - Google Patents
Digital phase locked loopInfo
- Publication number
- JPS6471351A JPS6471351A JP62228938A JP22893887A JPS6471351A JP S6471351 A JPS6471351 A JP S6471351A JP 62228938 A JP62228938 A JP 62228938A JP 22893887 A JP22893887 A JP 22893887A JP S6471351 A JPS6471351 A JP S6471351A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- phase comparison
- frame synchronizing
- stuff bit
- comparison signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To recover a timing clock signal whose jitter is remarkably reduced by generating a phase comparison signal from a frame synchronizing signal outputted from a frame synchronizing means and a stuff bit presence detection signal. CONSTITUTION:A frame synchronizing circuit 1 generates an interruption signal synchronously with a frame synchronizing signal to extract a clock signal. The clock signal and an output signal from a VCO 8 are fed to a phase comparator 3 to generate a phase comparison signal. The phase comparison signal and the stuff bit pressure detection signal outputted from the synchronizing circuit 1 are fed to a control section 7. The control section 7 takes in the phase comparison signal in proper timing during a period not affected by the frame synchronizing signal and the stuff bit presence detection signal. The voltage signal to be supplied to a VCO 6 is generated based on the taken-in phase comparison signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62228938A JPS6471351A (en) | 1987-09-11 | 1987-09-11 | Digital phase locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62228938A JPS6471351A (en) | 1987-09-11 | 1987-09-11 | Digital phase locked loop |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6471351A true JPS6471351A (en) | 1989-03-16 |
Family
ID=16884208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62228938A Pending JPS6471351A (en) | 1987-09-11 | 1987-09-11 | Digital phase locked loop |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6471351A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010527081A (en) * | 2007-05-15 | 2010-08-05 | クロノロジック ピーティーワイ リミテッド | USB-based synchronization and timing system |
-
1987
- 1987-09-11 JP JP62228938A patent/JPS6471351A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010527081A (en) * | 2007-05-15 | 2010-08-05 | クロノロジック ピーティーワイ リミテッド | USB-based synchronization and timing system |
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