KR970010287B1 - Digital processing phase locked loop - Google Patents

Digital processing phase locked loop Download PDF

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Publication number
KR970010287B1
KR970010287B1 KR94040182A KR19940040182A KR970010287B1 KR 970010287 B1 KR970010287 B1 KR 970010287B1 KR 94040182 A KR94040182 A KR 94040182A KR 19940040182 A KR19940040182 A KR 19940040182A KR 970010287 B1 KR970010287 B1 KR 970010287B1
Authority
KR
South Korea
Prior art keywords
frame pulse
multi frame
synchronizing
clock
unit
Prior art date
Application number
KR94040182A
Other languages
Korean (ko)
Other versions
KR960027354A (en
Inventor
Won-Sik Seo
Original Assignee
Lg Inf & Comm Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Inf & Comm Ltd filed Critical Lg Inf & Comm Ltd
Priority to KR94040182A priority Critical patent/KR970010287B1/en
Publication of KR960027354A publication Critical patent/KR960027354A/en
Application granted granted Critical
Publication of KR970010287B1 publication Critical patent/KR970010287B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The multi frame pulse and clock synchronous control device in a digital processing phase locked loop is comprised of: a reference multi frame pulse generator synchronizing the phase of an input clock to generate a reference multi frame pulse; a system multi frame pulse generator generating a multi frame pulse of an operation unit and a standby unit to the system clock; a reference clock phase synchronizing unit synchronizing the clock phase of the operation unit and the standby unit with the reference multi frame pulse obtained in the reference multi frame pulse generator; and a multi frame pulse phase synchronizing unit synchronizing the multi frame pulse of the operation unit and the standby unit according to the system multi frame pulse obtained in the system multi frame pulse generator.
KR94040182A 1994-12-30 1994-12-30 Digital processing phase locked loop KR970010287B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR94040182A KR970010287B1 (en) 1994-12-30 1994-12-30 Digital processing phase locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR94040182A KR970010287B1 (en) 1994-12-30 1994-12-30 Digital processing phase locked loop

Publications (2)

Publication Number Publication Date
KR960027354A KR960027354A (en) 1996-07-22
KR970010287B1 true KR970010287B1 (en) 1997-06-23

Family

ID=19406026

Family Applications (1)

Application Number Title Priority Date Filing Date
KR94040182A KR970010287B1 (en) 1994-12-30 1994-12-30 Digital processing phase locked loop

Country Status (1)

Country Link
KR (1) KR970010287B1 (en)

Also Published As

Publication number Publication date
KR960027354A (en) 1996-07-22

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