JPS6412746A - Timing extraction circuit - Google Patents

Timing extraction circuit

Info

Publication number
JPS6412746A
JPS6412746A JP62170614A JP17061487A JPS6412746A JP S6412746 A JPS6412746 A JP S6412746A JP 62170614 A JP62170614 A JP 62170614A JP 17061487 A JP17061487 A JP 17061487A JP S6412746 A JPS6412746 A JP S6412746A
Authority
JP
Japan
Prior art keywords
clock
phase
2foa
binary signal
foa
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62170614A
Other languages
Japanese (ja)
Other versions
JPH0650881B2 (en
Inventor
Toru Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62170614A priority Critical patent/JPH0650881B2/en
Publication of JPS6412746A publication Critical patent/JPS6412746A/en
Publication of JPH0650881B2 publication Critical patent/JPH0650881B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To generate a reception clock with a few amount of jitter at the time of transmitting data by a pair of cables, by comparing the phase of a clock outputted from a frequency division circuit with the phase of a clock outputted from a word synchronization circuit in the established state of synchronization. CONSTITUTION:When a binary signal 100 is inputted, a phase comparator 2 decides the lead or the lag of the phase of the binary signal 100 for a reference clock 2fOA in a digital phase locking oscillator A. A digital loop filter 3 controls the oscillation frequency of a digital voltage controlled oscillator 4 corresponding to the decided result of the phase comparator 2. The frequency divider 5 generates an fOA clock and a 2fOA clock by frequency-dividing the output 104 of the voltage controlled oscillator 4. The fOA clock and the 2fOA clock are synchronized with the binary signal 100. And when the fO rises synchronizing with the binary signal 100, the reference clock to perform phase comparison at the phase comparator 2 is switched from the 2fOA to the fOA by controlling a selector 8 by the output 107b of the word synchronization circuit 7.
JP62170614A 1987-07-07 1987-07-07 Timing extraction circuit Expired - Lifetime JPH0650881B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62170614A JPH0650881B2 (en) 1987-07-07 1987-07-07 Timing extraction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62170614A JPH0650881B2 (en) 1987-07-07 1987-07-07 Timing extraction circuit

Publications (2)

Publication Number Publication Date
JPS6412746A true JPS6412746A (en) 1989-01-17
JPH0650881B2 JPH0650881B2 (en) 1994-06-29

Family

ID=15908127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62170614A Expired - Lifetime JPH0650881B2 (en) 1987-07-07 1987-07-07 Timing extraction circuit

Country Status (1)

Country Link
JP (1) JPH0650881B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442223A (en) * 1990-10-17 1995-08-15 Nippondenso Co., Ltd. Semiconductor device with stress relief
GB2332857A (en) * 1998-01-06 1999-07-07 Keith Lyons Foldable clothes hanger

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442223A (en) * 1990-10-17 1995-08-15 Nippondenso Co., Ltd. Semiconductor device with stress relief
GB2332857A (en) * 1998-01-06 1999-07-07 Keith Lyons Foldable clothes hanger
GB2332857B (en) * 1998-01-06 2001-10-10 Keith Lyons A suspending device

Also Published As

Publication number Publication date
JPH0650881B2 (en) 1994-06-29

Similar Documents

Publication Publication Date Title
US5109394A (en) All digital phase locked loop
EP0347737A3 (en) Synchronisation method for a clock generator, especially of a clock generator of a digital telephone exchange
ES8705721A1 (en) Circuit arrangement for the synchronisation of a signal.
US4309662A (en) Circuit for rapidly resynchronizing a clock
US4706040A (en) Frequency synthesizer circuit
EP0147897A3 (en) Phase-locked loop capable of generating a plurality of stable frequency signals
AU1094199A (en) Phase-locked loop and method for automatically locking to a variable input frequency
JPH0519329B2 (en)
GB1348546A (en) Phase locked loop
US4689577A (en) Circuit for synchronizing an oscillator to a pulse train
GB2073515A (en) Frequency locked loop
JPS6412746A (en) Timing extraction circuit
US5537449A (en) Clock synchronizing circuitry having a fast tuning circuit
GB2291293A (en) Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop
HK35996A (en) Integratable phase-locked loop
JPS63204837A (en) Phase locked loop circuit
JPS6412691A (en) Video signal sampling circuit
JPS5535545A (en) Digital phase synchronous circuit
US3382453A (en) Circuit for stabilizing an oscillator during interruption of synchronizing signal
JPH06276089A (en) Pll circuit
GB2291548A (en) Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop
JPS5967730A (en) Pll circuit
JPS5620355A (en) Clock signal forming circuit
JPS6468127A (en) Oscillation circuit
JPS6429174A (en) Clock generation circuit