JPS6464433A - On-line monitor system - Google Patents

Abstract

PURPOSE:To decide coincidence and decidence between a transmitting data signaling and a returning data signal string regardless of the delay time of the returning data signal string by executing the decision of the coincidence and decidence between the transmitting data signal string and the returning data signal string in a prescribed way. CONSTITUTION:A memory circuit 31 stores the bit constitution of a transmitting data signal string A to be added while a timing signal (a) is '1'. Next, a parity detecting circuit 32 detects whether the number of '1' included in the transmitting data signal string while a timing signal (b) is '1' is an even number or not and outputs the detected result. On the other hand, a parity detecting circuit 35 detects whether the number of '1' included in the returning data signal string B to be added while a timing signal (c) is '1' is the even number or not and outputs the detected result. A parity check circuit 33 compares the detected results from the detecting circuits 32 and 35 in the falling of the output signal of a delay circuit 39 to slightly delay the timing signal (c) and when the results are coincident, an output signal (e) is made '0'. Then, when they are decident, the signal (e) is made '1'.