JPS6464072A - Image memory - Google Patents

Image memory

Info

Publication number
JPS6464072A
JPS6464072A JP62221693A JP22169387A JPS6464072A JP S6464072 A JPS6464072 A JP S6464072A JP 62221693 A JP62221693 A JP 62221693A JP 22169387 A JP22169387 A JP 22169387A JP S6464072 A JPS6464072 A JP S6464072A
Authority
JP
Japan
Prior art keywords
reading
register
random access
action
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62221693A
Other languages
Japanese (ja)
Inventor
Yasuo Masaki
Kimitoshi Hori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Minolta Co Ltd
Original Assignee
Minolta Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minolta Co Ltd filed Critical Minolta Co Ltd
Priority to JP62221693A priority Critical patent/JPS6464072A/en
Priority to US07/239,749 priority patent/US4912680A/en
Publication of JPS6464072A publication Critical patent/JPS6464072A/en
Pending legal-status Critical Current

Links

Landscapes

  • Image Input (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To perform simultaneous serial input and output actions and also to realize a random access action by connecting a reading register to each memory element together with both random and serial access buses connected to the reading register respectively. CONSTITUTION:An image memory contains memory elements M0-M7 and writing registers WR0-WR7 are connected to the input parts of elements M0-M7 together with the reading registers RR0-RR7 connected to the output parts of elements M0-M7 respectively. Then a random access bus 1 and a serial access bus 2 are connected to those registers WR0-WR7 and RR0-RR7 respectively. Then the selected writing register WRi (i=0-7) is set under an output state and a write signal is applied to the memory element Mi corresponding to the register WRi. Thus a random access writing action is secured. At the same time, the only memory element Mi is set under a reading state and only the corresponding reading register RRi is set under an output state. Thus a random access reading action is secured.
JP62221693A 1987-09-03 1987-09-03 Image memory Pending JPS6464072A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62221693A JPS6464072A (en) 1987-09-03 1987-09-03 Image memory
US07/239,749 US4912680A (en) 1987-09-03 1988-09-02 Image memory having plural input registers and output registers to provide random and serial accesses

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62221693A JPS6464072A (en) 1987-09-03 1987-09-03 Image memory

Publications (1)

Publication Number Publication Date
JPS6464072A true JPS6464072A (en) 1989-03-09

Family

ID=16770797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62221693A Pending JPS6464072A (en) 1987-09-03 1987-09-03 Image memory

Country Status (1)

Country Link
JP (1) JPS6464072A (en)

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