JPS6462872A - Data recording and reproducing device - Google Patents

Data recording and reproducing device

Info

Publication number
JPS6462872A
JPS6462872A JP21790987A JP21790987A JPS6462872A JP S6462872 A JPS6462872 A JP S6462872A JP 21790987 A JP21790987 A JP 21790987A JP 21790987 A JP21790987 A JP 21790987A JP S6462872 A JPS6462872 A JP S6462872A
Authority
JP
Japan
Prior art keywords
data
buffer
reproducing
recording
executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21790987A
Other languages
Japanese (ja)
Inventor
Kazutaka Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP21790987A priority Critical patent/JPS6462872A/en
Publication of JPS6462872A publication Critical patent/JPS6462872A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To speedily realize a verify processing with minimizing a cost by judging reproducing data and recording data accumulated in a data buffer for the unit of data transferring. CONSTITUTION:The titled device equips with a comparing means to judge whether the reproducing data and the recording data accumulated in the data buffer are coincident or not for the unit of the data transferring from the data buffer to a data recording and reproducing means and a holding means to hold the compared result of this comparing means. Namely, a comparator 5 is provided to compare data read from a buffer memory 1 and data read from an error correcting circuit 2 and verify operation is executed with utilizing a DMAC3 to transfer the accumulating data of the buffer memory 1 to the error correcting circuit 2. Thus, the verify operation can be executed at the extremely high speed.
JP21790987A 1987-09-02 1987-09-02 Data recording and reproducing device Pending JPS6462872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21790987A JPS6462872A (en) 1987-09-02 1987-09-02 Data recording and reproducing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21790987A JPS6462872A (en) 1987-09-02 1987-09-02 Data recording and reproducing device

Publications (1)

Publication Number Publication Date
JPS6462872A true JPS6462872A (en) 1989-03-09

Family

ID=16711650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21790987A Pending JPS6462872A (en) 1987-09-02 1987-09-02 Data recording and reproducing device

Country Status (1)

Country Link
JP (1) JPS6462872A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536215A (en) * 1991-01-22 1993-02-12 Samsung Electron Co Ltd Data recorder and its method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536215A (en) * 1991-01-22 1993-02-12 Samsung Electron Co Ltd Data recorder and its method

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