JPS6462717A - Microprocessor system - Google Patents

Microprocessor system

Info

Publication number
JPS6462717A
JPS6462717A JP21972487A JP21972487A JPS6462717A JP S6462717 A JPS6462717 A JP S6462717A JP 21972487 A JP21972487 A JP 21972487A JP 21972487 A JP21972487 A JP 21972487A JP S6462717 A JPS6462717 A JP S6462717A
Authority
JP
Japan
Prior art keywords
bus
subordinate device
microprocessor
stop control
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21972487A
Other languages
Japanese (ja)
Inventor
Shigeru Kimura
Takeyoshi Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP21972487A priority Critical patent/JPS6462717A/en
Publication of JPS6462717A publication Critical patent/JPS6462717A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To insert or draw out a bus subordinate device without exerting an undesirable influence on other bus subordinate device, by providing an operation stop control circuit of a microprocessor, and a high impedance switching circuit of a microprocessor bus. CONSTITUTION:For instance, at the time of inserting or drawing out a second bus subordinate device 3, when an operation stop control switch 5 of an operation stop control circuit 4 provided in a microprocessor loading device 1 is operated in advance, a stop holding circuit 6 is set, and by an output of a stop control signal line 12, a microprocessor bus 13 extended from a microprocessor 1a becomes a high impedance state. Also, the stop control signal line 12 inhibits a write gate circuit 9 provided in a first bus subordinate device 2. In such a way, a malfunction of the first bus subordinate device 2, caused by a noise generated at the time of inserting or drawing out the second bus subordinate device 3 is prevented, and also, even in other bus subordinate device, its write gate gate circuit is inhibited, and a malfunction is prevented.
JP21972487A 1987-09-02 1987-09-02 Microprocessor system Pending JPS6462717A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21972487A JPS6462717A (en) 1987-09-02 1987-09-02 Microprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21972487A JPS6462717A (en) 1987-09-02 1987-09-02 Microprocessor system

Publications (1)

Publication Number Publication Date
JPS6462717A true JPS6462717A (en) 1989-03-09

Family

ID=16739974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21972487A Pending JPS6462717A (en) 1987-09-02 1987-09-02 Microprocessor system

Country Status (1)

Country Link
JP (1) JPS6462717A (en)

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