JPS6461846A - Priority control system - Google Patents

Priority control system

Info

Publication number
JPS6461846A
JPS6461846A JP21936187A JP21936187A JPS6461846A JP S6461846 A JPS6461846 A JP S6461846A JP 21936187 A JP21936187 A JP 21936187A JP 21936187 A JP21936187 A JP 21936187A JP S6461846 A JPS6461846 A JP S6461846A
Authority
JP
Japan
Prior art keywords
memory access
flags
access requests
priority level
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21936187A
Other languages
Japanese (ja)
Inventor
Makoto Sekine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21936187A priority Critical patent/JPS6461846A/en
Publication of JPS6461846A publication Critical patent/JPS6461846A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Abstract

PURPOSE:To realize the memory access processing in response to the priority level, by changing the number of memory access requests of higher priority levels which is selected within a specific unit time via a selection circuit so that the priority order is controlled for memory access. CONSTITUTION:The flags 141a-141f of all memory access requests and the priority information 142a-142f to be added to said flags are supplied to a selection circuit 146'. Thus all access requests are selected at the same rate in the order of flags 141a-141d as long as the priority levels are equal to each other. Under such conditions, an access signal of a high priority level is defined as the flag 141a. Thus the number of memory access requests of high priority levels which are selected within a specific time are changed like 141a 141b 141c 141a 141d 141e 141f. As a result, the flag 141a of a high priority level is selected at a rate double as high as other flags. Then a memory access request of a high priority level is selected in preference to others.
JP21936187A 1987-09-02 1987-09-02 Priority control system Pending JPS6461846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21936187A JPS6461846A (en) 1987-09-02 1987-09-02 Priority control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21936187A JPS6461846A (en) 1987-09-02 1987-09-02 Priority control system

Publications (1)

Publication Number Publication Date
JPS6461846A true JPS6461846A (en) 1989-03-08

Family

ID=16734227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21936187A Pending JPS6461846A (en) 1987-09-02 1987-09-02 Priority control system

Country Status (1)

Country Link
JP (1) JPS6461846A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671530A (en) * 1995-10-30 1997-09-30 Delco Electronics Corporation Flip-chip mounting assembly and method with vertical wafer feeder
US7689781B2 (en) 2002-02-26 2010-03-30 Nxp B.V. Access to a collective resource in which low priority functions are grouped, read accesses of the group being given higher priority than write accesses of the group
JP2014220017A (en) * 2014-08-28 2014-11-20 富士通株式会社 Arbitration circuit, control method, and control program

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52133733A (en) * 1976-04-30 1977-11-09 Mitsubishi Electric Corp Scanning system
JPS56166559A (en) * 1980-05-28 1981-12-21 Hitachi Ltd Precedence selecting device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52133733A (en) * 1976-04-30 1977-11-09 Mitsubishi Electric Corp Scanning system
JPS56166559A (en) * 1980-05-28 1981-12-21 Hitachi Ltd Precedence selecting device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671530A (en) * 1995-10-30 1997-09-30 Delco Electronics Corporation Flip-chip mounting assembly and method with vertical wafer feeder
US7689781B2 (en) 2002-02-26 2010-03-30 Nxp B.V. Access to a collective resource in which low priority functions are grouped, read accesses of the group being given higher priority than write accesses of the group
JP2014220017A (en) * 2014-08-28 2014-11-20 富士通株式会社 Arbitration circuit, control method, and control program

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