GB1482819A - Addressing device for a programme stored data processing system - Google Patents
Addressing device for a programme stored data processing systemInfo
- Publication number
- GB1482819A GB1482819A GB2671175A GB2671175A GB1482819A GB 1482819 A GB1482819 A GB 1482819A GB 2671175 A GB2671175 A GB 2671175A GB 2671175 A GB2671175 A GB 2671175A GB 1482819 A GB1482819 A GB 1482819A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory
- address
- read
- order part
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Stored Programmes (AREA)
Abstract
1482819 Memory addressing INTERNATIONAL STANDARD ELECTRIC CORP 24 June 1975 [28 June 1974] 26711/75 Heading G4A An arrangement for selectively modifying memory addresses involving look up in read only memories is described. A processor supplies a program address having higher H and lower L order parts specifying a table base and a word location within a table in a memory 6 having a read only part for program instructions and a read/write part for data. The processor or a device including a comparator compares the high order part H with the address of the boundary between the read only and read/write parts of memory 6 and produces for each supplied address a signal DA or DA indicating data and an instruction respectively. For an instruction, signal DA enables read only memory 1 which is addressed by the high order part H to read out the corresponding page address in memory 6, which, together with the unchanged low order part L via selector 7, addresses memory 6. For data, signal DA causes read only memories 2 and 3 to be addressed with the high order part H to read out the page address in memory 6 containing the table which contains the desired word and the location in that page of the first word of the table respectively. The output of memory 3 is added at 4 to the low order part L of the address to form the low order part of the address of the required word to be supplied to memory 6, any carry R being added at 5 to the page address read from memory 2 to form the high order part of the address for memory 6. The read only memories 1-3 may be programmable devices which can be altered, e.g. as integrated circuits forming the ROM part of memory 6 are relocated. In a modification program addresses relating to, e.g. programs common to a number of users are supplied directly to memory 6. The address modification, with its attendant delays, is used when the supplied address relates to data or to a program particular to a particular user. In such cases a comparator acting on the high order part H of a supplied address determines whether address modification is required.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7422637A FR2276636A1 (en) | 1974-06-28 | 1974-06-28 | DEVICE FOR ADDRESSING THE MEMORY OF A REGISTERED PROGRAM CONTROL SYSTEM |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1482819A true GB1482819A (en) | 1977-08-17 |
Family
ID=9140672
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2671175A Expired GB1482819A (en) | 1974-06-28 | 1975-06-24 | Addressing device for a programme stored data processing system |
Country Status (4)
Country | Link |
---|---|
BE (1) | BE830717A (en) |
DE (1) | DE2528164A1 (en) |
FR (1) | FR2276636A1 (en) |
GB (1) | GB1482819A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0037875A1 (en) * | 1980-04-10 | 1981-10-21 | Siemens Nixdorf Informationssysteme Aktiengesellschaft | Modular data processing system |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2445989B1 (en) * | 1979-01-02 | 1987-06-26 | Honeywell Inf Systems | PRIORITY DETERMINATION AND INTERRUPTION DEVICE OF A DATA PROCESSING SYSTEM |
FR2515404B1 (en) * | 1981-10-28 | 1987-06-26 | France Etat | PROCESSOR MEMORY MANAGEMENT ASSEMBLY |
-
1974
- 1974-06-28 FR FR7422637A patent/FR2276636A1/en active Granted
-
1975
- 1975-06-24 DE DE19752528164 patent/DE2528164A1/en active Pending
- 1975-06-24 GB GB2671175A patent/GB1482819A/en not_active Expired
- 1975-06-27 BE BE2054429A patent/BE830717A/en unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0037875A1 (en) * | 1980-04-10 | 1981-10-21 | Siemens Nixdorf Informationssysteme Aktiengesellschaft | Modular data processing system |
Also Published As
Publication number | Publication date |
---|---|
FR2276636B1 (en) | 1977-10-07 |
FR2276636A1 (en) | 1976-01-23 |
BE830717A (en) | 1975-12-29 |
DE2528164A1 (en) | 1976-01-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
746 | Register noted 'licences of right' (sect. 46/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |