JPS6459964A - Hetero-junction fet - Google Patents

Hetero-junction fet

Info

Publication number
JPS6459964A
JPS6459964A JP21750187A JP21750187A JPS6459964A JP S6459964 A JPS6459964 A JP S6459964A JP 21750187 A JP21750187 A JP 21750187A JP 21750187 A JP21750187 A JP 21750187A JP S6459964 A JPS6459964 A JP S6459964A
Authority
JP
Japan
Prior art keywords
layer
nondoped
thickness
gate
built
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21750187A
Other languages
Japanese (ja)
Inventor
Masahisa Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21750187A priority Critical patent/JPS6459964A/en
Publication of JPS6459964A publication Critical patent/JPS6459964A/en
Pending legal-status Critical Current

Links

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To improve the breakdown strength of a gate by a method wherein a nondoped channel layer, an electron supply layer and a nondoped barrier layer are successively built up on a compound semiconductor substrate and a gate electrode is built up on them to provide a gate-channel structure. CONSTITUTION:A nondoped GaAs channel layer 2 with a thickness of 1mum, an Si-doped electron supply layer 3 with a thickness of 200Angstrom , a nondoped barri er layer 3 with a thickness of 200Angstrom and an Si-doped n-type GaAs ohmic contact layer 5 with a thickness of 600Angstrom are built up on a GaAs substrate 1 by a molec ular beam epitaxy method. Composite metal films are applied by a vacuum evaporation method and then alloyed by heating at 450 deg.C for one minute to form a source electrode 7 and a drain electrode 8. The surface of the barrier layer 4 is exposed by selective etching and a gate electrode 6 is formed on it by vacuum evaporation. With this constitution, the activation rate of the electron supply layer is not degraded and, moreover, the breakdown strength of the gate can be improved.
JP21750187A 1987-08-31 1987-08-31 Hetero-junction fet Pending JPS6459964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21750187A JPS6459964A (en) 1987-08-31 1987-08-31 Hetero-junction fet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21750187A JPS6459964A (en) 1987-08-31 1987-08-31 Hetero-junction fet

Publications (1)

Publication Number Publication Date
JPS6459964A true JPS6459964A (en) 1989-03-07

Family

ID=16705224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21750187A Pending JPS6459964A (en) 1987-08-31 1987-08-31 Hetero-junction fet

Country Status (1)

Country Link
JP (1) JPS6459964A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02240937A (en) * 1989-03-14 1990-09-25 Matsushita Electron Corp Field-effect transistor
JPH04175203A (en) * 1990-11-08 1992-06-23 Fuji Electric Co Ltd Water-cooled type ozonizer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02240937A (en) * 1989-03-14 1990-09-25 Matsushita Electron Corp Field-effect transistor
JPH04175203A (en) * 1990-11-08 1992-06-23 Fuji Electric Co Ltd Water-cooled type ozonizer

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