JPS6458124A - A/d conversion circuit - Google Patents

A/d conversion circuit

Info

Publication number
JPS6458124A
JPS6458124A JP21435587A JP21435587A JPS6458124A JP S6458124 A JPS6458124 A JP S6458124A JP 21435587 A JP21435587 A JP 21435587A JP 21435587 A JP21435587 A JP 21435587A JP S6458124 A JPS6458124 A JP S6458124A
Authority
JP
Japan
Prior art keywords
counter
vco
count
fluctuation
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21435587A
Other languages
Japanese (ja)
Inventor
Shinichi Oe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21435587A priority Critical patent/JPS6458124A/en
Publication of JPS6458124A publication Critical patent/JPS6458124A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To eliminate the effect of a characteristic change in the voltage versus frequency due to temperature fluctuation of a voltage controlled oscillation circuit (VCO), power voltage fluctuation and process fluctuation by using a couple of VCOs so as to obtain the relative value of mutual oscillation characteristics. CONSTITUTION:The titled A/D conversion circuit consists of 1st and 2nd VCOs 1, 2, 1st and 2nd counters 5, 6 and a control circuit 4. A frequency fk in response to the reference voltage is generated by the 2nd VCO 2 and up to 2<n> is counted by the 2nd counter 6. A frequency fin in response to the input is generated by the 1st VCO 1 and counted by the 1st counter 5. The control circuit 4 starts the count of the 1st and 2nd counters 5, 6 simultaneously and when the 2nd counter 6 counts by 2<n>, the count of the 1st counter 5 is stopped. In this case, let the count result of the 1st counter 5 be N, the count result N of the 1st counter 5 gives n-bit A/D conversion output.
JP21435587A 1987-08-28 1987-08-28 A/d conversion circuit Pending JPS6458124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21435587A JPS6458124A (en) 1987-08-28 1987-08-28 A/d conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21435587A JPS6458124A (en) 1987-08-28 1987-08-28 A/d conversion circuit

Publications (1)

Publication Number Publication Date
JPS6458124A true JPS6458124A (en) 1989-03-06

Family

ID=16654406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21435587A Pending JPS6458124A (en) 1987-08-28 1987-08-28 A/d conversion circuit

Country Status (1)

Country Link
JP (1) JPS6458124A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006126338A1 (en) 2005-05-27 2006-11-30 Fuetrek Co., Ltd Analog/digital converter
US20150311909A1 (en) * 2014-04-29 2015-10-29 Honeywell International Inc. Converter for analog inputs

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006126338A1 (en) 2005-05-27 2006-11-30 Fuetrek Co., Ltd Analog/digital converter
EP1885068A1 (en) * 2005-05-27 2008-02-06 Fuetrek Co. Ltd. Analog/digital converter
EP1885068A4 (en) * 2005-05-27 2008-11-05 Fuetrek Co Ltd Analog/digital converter
US20150311909A1 (en) * 2014-04-29 2015-10-29 Honeywell International Inc. Converter for analog inputs
US9246501B2 (en) * 2014-04-29 2016-01-26 Honeywell International Inc. Converter for analog inputs

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