JPS6457658U - - Google Patents
Info
- Publication number
- JPS6457658U JPS6457658U JP15014487U JP15014487U JPS6457658U JP S6457658 U JPS6457658 U JP S6457658U JP 15014487 U JP15014487 U JP 15014487U JP 15014487 U JP15014487 U JP 15014487U JP S6457658 U JPS6457658 U JP S6457658U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- circuit element
- semiconductor
- junction
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Description
第１図および第２図が本考案に関し、第１図は
本考案による半導体回路素子をダイオードについ
て示すその完成時および主な製作工程中の状態を
示す断面図、第２図は半導体回路素子がトランジ
スタである場合の完成時および製作中の状態を示
す断面図である。第３図は従来技術による半導体
回路素子をダイオードについて示す完成時および
製作中の断面図である。図において、
１：半導体基体、２：埋込拡散層、３：エピタ
キシヤル層、４：分離層、５：酸化膜、６：窒化
膜、７：酸化膜、８：レジスト膜、９：ｐ形層、
１０：エミツタ層、１１，１２：接続層、１３：
接続膜、１４：ｐｎ接合、１４ａ：空乏層、２０
：第一の半導体層、２１：凹所、２２：凹所の底
面、２３：凹所の斜側面、３０：第二の半導体層
、３０ａ：不純物、４０：主接合としてのｐｎ接
合、４１：空乏層、５０：回路素子としてのダイ
オード、５１：回路素子としてのトランジスタ、
Ｂ：ベース、Ｃ：コレクタ、Ｅ：エミツタ、Ｒ，
ｒ：ｐ形層の屈曲部の曲率半径、である。
Figures 1 and 2 relate to the present invention; Figure 1 is a cross-sectional view showing the semiconductor circuit element according to the present invention as a diode at the time of completion and during the main manufacturing process; FIG. 3 is a cross-sectional view showing a transistor when it is completed and when it is being manufactured. FIG. 3 is a cross-sectional view of a semiconductor circuit element according to the prior art, showing a diode as completed and during fabrication. In the figure, 1: semiconductor substrate, 2: buried diffusion layer, 3: epitaxial layer, 4: isolation layer, 5: oxide film, 6: nitride film, 7: oxide film, 8: resist film, 9: p-type layer,
10: Emitter layer, 11, 12: Connection layer, 13:
Connection film, 14: pn junction, 14a: depletion layer, 20
: first semiconductor layer, 21: recess, 22: bottom surface of recess, 23: oblique side surface of recess, 30: second semiconductor layer, 30a: impurity, 40: pn junction as main junction, 41: Depletion layer, 50: diode as a circuit element, 51: transistor as a circuit element,
B: Base, C: Collector, E: Emitter, R,
r: radius of curvature of the bent portion of the p-type layer.
Claims (1)
作する回路素子であつて、基体の主面側に位置す
る一方の導電形をもつ第一の半導体層と、該第一
の半導体層の表面から堀り込まれた皿状の凹所の
底面およびそれと鈍角をなす斜側面とを含む領域
の表面から第一の半導体層内に所定の深さで拡散
された他方の導電形をもつ第二の半導体層と、第
一の半導体層と第二の半導体層との間に形成され
るｐｎ接合とを少なくとも含んでなり、ｐｎ接合
を回路素子の主接合として回路素子が非導通状態
にあるときに回路電圧が掛かるように第一の半導
体層および第二の半導体層がそれぞれ接続されて
なる半導体回路素子。 A circuit element built into a semiconductor substrate and operated at a predetermined circuit voltage, including a first semiconductor layer having one conductivity type located on the main surface side of the substrate, and a first semiconductor layer from the surface of the first semiconductor layer. A second conductivity type having the other conductivity type is diffused into the first semiconductor layer to a predetermined depth from the surface of the region including the bottom surface of the dish-shaped recess and the obtuse side surface forming an obtuse angle thereto. It includes at least a semiconductor layer and a pn junction formed between the first semiconductor layer and the second semiconductor layer, and the pn junction is the main junction of the circuit element when the circuit element is in a non-conducting state. A semiconductor circuit element in which a first semiconductor layer and a second semiconductor layer are connected to each other so that a circuit voltage is applied thereto.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15014487U JPS6457658U (en) | 1987-09-30 | 1987-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15014487U JPS6457658U (en) | 1987-09-30 | 1987-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6457658U true JPS6457658U (en) | 1989-04-10 |
Family
ID=31423019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15014487U Pending JPS6457658U (en) | 1987-09-30 | 1987-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6457658U (en) |
-
1987
- 1987-09-30 JP JP15014487U patent/JPS6457658U/ja active Pending
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