UST104803I4 - Self-aligned process for providing an improved high performance bipolar transistor - Google Patents
Self-aligned process for providing an improved high performance bipolar transistor Download PDFInfo
- Publication number
- UST104803I4 UST104803I4 US06/580,962 US58096284A UST104803I4 US T104803 I4 UST104803 I4 US T104803I4 US 58096284 A US58096284 A US 58096284A US T104803 I4 UST104803 I4 US T104803I4
- Authority
- US
- United States
- Prior art keywords
- epitaxial layer
- isolation trench
- oxide isolation
- recessed oxide
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 abstract 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 3
- 229920005591 polysilicon Polymers 0.000 abstract 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 239000002131 composite material Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
A bipolar transistor structure formed in a monolithic silicon semiconductor substrate of p type having a planar surface comprising: a subcollector of n type formed in the substrate; an epitaxial layer of n type formed on said planar surface of said substrate and also having a planar surface, the epitaxial layer having a thickness in the order of 1.0 to 1.5 micrometers; an enclosed deep recessed oxide isolation trench enclosing a transistor structure area of the substrate and the epitaxial layer, the enclosed deep recessed oxide isolation trench having a depth extending from said planar surface of said epitaxial layer through the subcollector region; a shallow recessed oxide isolation trench, the relatively shallow recessed oxide isolation trench being wholly enclosed by the deep recessed oxide isolation trench and intersecting the deep recessed oxide isolation trench at two spaced apart points to divide said transistor structure area enclosed by the deep recessed oxide isolation trench into first and second areas, the first and second areas being electrically connected one to the other by the subcollector region;
a shallow depth emitter region formed in a limited portion of the first area of said epitaxial layer, the emitter region having a depth in the order of 0.1 micrometers;
an active base region formed beneath said emitter region in the limited portion the first area of said epitaxial layer, the active base region having a width in the order of 0.1 micrometers;
an inactive base region surrounding the emitter region and active base region, the inactive base region being wholly contained within the first area of said epitaxial layer;
an emitter-base junction contained within said first area of the epitaxial layer and extending to the surface of the epitaxial layer;
a composite layer of silicon dioxide and silicon nitride having a width of approximately 0.2 to 0.3 micrometers, the composite layer being positioned on the planar surface of the epitaxial layer over the surface juncture of said emitter-base junction, the silicon dioxide having a thickness of approximately 500Å and the silicon nitride layer having a thickness of approximately 500Å;
the second area of the epitaxial layer containing a collector reach through, the shallow recessed oxide isolation trench isolating the collector reach through from the inactive base region;
a layer of polysilicon p type on said planar surface of the epitaxial layer and in physical and electrical contact with the inactive base region, the polysilicon layer extending over a portion of said enclosed relatively deep recessed oxide isolation trench; and,
a base contact physically and electrically contacting the portion of the polysilicon layer which extends over the enclosed deep recessed oxide isolation trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/580,962 UST104803I4 (en) | 1981-07-13 | 1984-02-16 | Self-aligned process for providing an improved high performance bipolar transistor |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US28236581A | 1981-07-13 | 1981-07-13 | |
| US06/580,962 UST104803I4 (en) | 1981-07-13 | 1984-02-16 | Self-aligned process for providing an improved high performance bipolar transistor |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US28236581A Continuation | 1981-07-13 | 1981-07-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UST104803I4 true UST104803I4 (en) | 1984-11-06 |
Family
ID=26961399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US06/580,962 Pending UST104803I4 (en) | 1981-07-13 | 1984-02-16 | Self-aligned process for providing an improved high performance bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | UST104803I4 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0293641A1 (en) * | 1987-05-21 | 1988-12-07 | Siemens Aktiengesellschaft | Process for the manufacture of a full self-aligned bipolar transistor |
| US5234846A (en) * | 1992-04-30 | 1993-08-10 | International Business Machines Corporation | Method of making bipolar transistor with reduced topography |
| US6483163B2 (en) | 1997-09-02 | 2002-11-19 | Nikon Corporation | Photoelectric conversion devices and photoelectric conversion apparatus employing the same |
-
1984
- 1984-02-16 US US06/580,962 patent/UST104803I4/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0293641A1 (en) * | 1987-05-21 | 1988-12-07 | Siemens Aktiengesellschaft | Process for the manufacture of a full self-aligned bipolar transistor |
| US4829015A (en) * | 1987-05-21 | 1989-05-09 | Siemens Aktiengesellschaft | Method for manufacturing a fully self-adjusted bipolar transistor |
| US5234846A (en) * | 1992-04-30 | 1993-08-10 | International Business Machines Corporation | Method of making bipolar transistor with reduced topography |
| US6483163B2 (en) | 1997-09-02 | 2002-11-19 | Nikon Corporation | Photoelectric conversion devices and photoelectric conversion apparatus employing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| STPP | Information on status: patent application and granting procedure in general |
Free format text: DEFENSIVE PUBLICATION OR SIR FILE |