JPS6457643U - - Google Patents

Info

Publication number
JPS6457643U
JPS6457643U JP1987150142U JP15014287U JPS6457643U JP S6457643 U JPS6457643 U JP S6457643U JP 1987150142 U JP1987150142 U JP 1987150142U JP 15014287 U JP15014287 U JP 15014287U JP S6457643 U JPS6457643 U JP S6457643U
Authority
JP
Japan
Prior art keywords
bumps
integrated circuit
simulated
mounting structure
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987150142U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987150142U priority Critical patent/JPS6457643U/ja
Publication of JPS6457643U publication Critical patent/JPS6457643U/ja
Pending legal-status Critical Current

Links

Classifications

    • H10W70/60—
    • H10W90/724—

Landscapes

  • Wire Bonding (AREA)
JP1987150142U 1987-09-30 1987-09-30 Pending JPS6457643U (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987150142U JPS6457643U (enExample) 1987-09-30 1987-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987150142U JPS6457643U (enExample) 1987-09-30 1987-09-30

Publications (1)

Publication Number Publication Date
JPS6457643U true JPS6457643U (enExample) 1989-04-10

Family

ID=31423015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987150142U Pending JPS6457643U (enExample) 1987-09-30 1987-09-30

Country Status (1)

Country Link
JP (1) JPS6457643U (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE39603E1 (en) 1994-09-30 2007-05-01 Nec Corporation Process for manufacturing semiconductor device and semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE39603E1 (en) 1994-09-30 2007-05-01 Nec Corporation Process for manufacturing semiconductor device and semiconductor wafer

Similar Documents

Publication Publication Date Title
JP2755252B2 (ja) 半導体装置用パッケージ及び半導体装置
JPH022842U (enExample)
US5909055A (en) Chip package device mountable on a mother board in whichever of facedown and wire bonding manners
JPS6457643U (enExample)
JPS5849637Y2 (ja) 厚膜配線板
JPS6338328U (enExample)
JPH0448661U (enExample)
JPH0543476Y2 (enExample)
JP2880817B2 (ja) 半導体集積回路装置
JPH0466780U (enExample)
JPS59109150U (ja) Ｉｃチツプ用パツケ−ジ
JPS61153374U (enExample)
JPH0189752U (enExample)
JPS6214751U (enExample)
JPS6192064U (enExample)
JPH0338633U (enExample)
JPH01121945U (enExample)
JPS6336077U (enExample)
JPS6429872U (enExample)
JPS6113994U (ja) 電子装置
JP2001044320A (ja) 半導体チップ搭載基板
JPS6260034U (enExample)
JPS62197866U (enExample)
JPH0292934U (enExample)
JPH03120749A (ja) 半導体素子パッケージ