JPS6455968A - Block line timing generation circuit - Google Patents

Block line timing generation circuit

Info

Publication number
JPS6455968A
JPS6455968A JP21141287A JP21141287A JPS6455968A JP S6455968 A JPS6455968 A JP S6455968A JP 21141287 A JP21141287 A JP 21141287A JP 21141287 A JP21141287 A JP 21141287A JP S6455968 A JPS6455968 A JP S6455968A
Authority
JP
Japan
Prior art keywords
block line
frames
gate
generation circuit
once
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21141287A
Other languages
Japanese (ja)
Inventor
Yuji Takenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21141287A priority Critical patent/JPS6455968A/en
Publication of JPS6455968A publication Critical patent/JPS6455968A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To share a line/frame counter as it is, to miniaturize a circuit scale and to reduce cost by permitting an inhibition gate to stop transmitting a block line clock once after (n) frames. CONSTITUTION:If a four frame counter 33 terminates counting fourth frames, the output of a NAND gate 332 shows '0', and the block line clock appearing in the output of an OR gate in a logical gate circuit 341 is reduced once every four frames. Thus, the block line clock BLC' which has been inhibited once every four frames is inputted to a block line counter 351, and the ripple carrier RC makes an objective block line timing signal (B1-B1-B1-B1 B2-B2-B2-B2 ...) TIM. Furthermore, the ripple carrier RC is waveform-shaped by a D flip flop 26. Thus, the block line timing generation circuit which is effective for miniaturizing and reducing cost compared to a conventional one can be realized.
JP21141287A 1987-08-27 1987-08-27 Block line timing generation circuit Pending JPS6455968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21141287A JPS6455968A (en) 1987-08-27 1987-08-27 Block line timing generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21141287A JPS6455968A (en) 1987-08-27 1987-08-27 Block line timing generation circuit

Publications (1)

Publication Number Publication Date
JPS6455968A true JPS6455968A (en) 1989-03-02

Family

ID=16605528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21141287A Pending JPS6455968A (en) 1987-08-27 1987-08-27 Block line timing generation circuit

Country Status (1)

Country Link
JP (1) JPS6455968A (en)

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